View source for 18168504. COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH CONDUCTIVE THROUGH SUBSTRATE LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

=COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH CONDUCTIVE THROUGH SUBSTRATE LAYER=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Company, Ltd.|Taiwan Semiconductor Manufacturing Company, Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Company, Ltd.]]

==Inventor(s)==

[[:Category:Wei-Xiang You of Hsinchu (TW)|Wei-Xiang You of Hsinchu (TW)]][[Category:Wei-Xiang You of Hsinchu (TW)]]

[[:Category:Wei-De Ho of Hsinchu (TW)|Wei-De Ho of Hsinchu (TW)]][[Category:Wei-De Ho of Hsinchu (TW)]]

[[:Category:Hsin Yang Hung of Hsinchu (TW)|Hsin Yang Hung of Hsinchu (TW)]][[Category:Hsin Yang Hung of Hsinchu (TW)]]

[[:Category:Meng-Yu Lin of Hsinchu (TW)|Meng-Yu Lin of Hsinchu (TW)]][[Category:Meng-Yu Lin of Hsinchu (TW)]]

[[:Category:Hsiang-Hung Huang of Hsinchu (TW)|Hsiang-Hung Huang of Hsinchu (TW)]][[Category:Hsiang-Hung Huang of Hsinchu (TW)]]

[[:Category:Chun-Fu Cheng of Hsinchu (TW)|Chun-Fu Cheng of Hsinchu (TW)]][[Category:Chun-Fu Cheng of Hsinchu (TW)]]

[[:Category:Kuan-Kan Hu of Hsinchu (TW)|Kuan-Kan Hu of Hsinchu (TW)]][[Category:Kuan-Kan Hu of Hsinchu (TW)]]

[[:Category:Szu-Hua Chen of Hsinchu (TW)|Szu-Hua Chen of Hsinchu (TW)]][[Category:Szu-Hua Chen of Hsinchu (TW)]]

[[:Category:Ting-Yun Wu of Hsinchu (TW)|Ting-Yun Wu of Hsinchu (TW)]][[Category:Ting-Yun Wu of Hsinchu (TW)]]

[[:Category:Wei-Cheng Tzeng of Hsinchu (TW)|Wei-Cheng Tzeng of Hsinchu (TW)]][[Category:Wei-Cheng Tzeng of Hsinchu (TW)]]

[[:Category:Wei-Cheng Lin of Hsinchu (TW)|Wei-Cheng Lin of Hsinchu (TW)]][[Category:Wei-Cheng Lin of Hsinchu (TW)]]

[[:Category:Cheng-Yin Wang of Hsinchu (TW)|Cheng-Yin Wang of Hsinchu (TW)]][[Category:Cheng-Yin Wang of Hsinchu (TW)]]

[[:Category:Jui-Chien Huang of Hsinchu (TW)|Jui-Chien Huang of Hsinchu (TW)]][[Category:Jui-Chien Huang of Hsinchu (TW)]]

[[:Category:Szuya Liao of Hsinchu (TW)|Szuya Liao of Hsinchu (TW)]][[Category:Szuya Liao of Hsinchu (TW)]]

==COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH CONDUCTIVE THROUGH SUBSTRATE LAYER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18168504 titled 'COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH CONDUCTIVE THROUGH SUBSTRATE LAYER

==Simplified Explanation==

The abstract describes a device with a complementary transistor structure, including a first transistor and a second transistor stacked on top of each other. The device also includes source/drain regions, source/drain contacts, gate isolation structure, and an interconnect structure.

* The device includes a complementary transistor structure with overlapping source/drain regions.
* It has source/drain contacts electrically coupled to the source/drain regions.
* There is a gate isolation structure adjacent to the transistors.
* An interconnect structure is electrically coupled to the source/drain contacts.
* The interconnect structure includes a conductive layer and a dielectric layer.

Potential applications of this technology:
* Integrated circuits
* Semiconductor devices
* Transistor technology

Problems solved by this technology:
* Improved performance of complementary transistors
* Enhanced electrical coupling between source/drain regions and contacts
* Efficient interconnect structure design

Benefits of this technology:
* Higher efficiency in electronic devices
* Better integration of components in semiconductor devices
* Enhanced overall performance of the device


==Original Abstract Submitted==

A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.



[[Category:H01L29/06]]
[[Category:H01L21/8238]]
[[Category:H01L23/528]]
[[Category:H01L29/417]]
[[Category:H01L29/423]]
[[Category:H01L29/786]]