18163146. MEMORY CIRCUIT ARCHITECTURE simplified abstract (QUALCOMM Incorporated)

MEMORY CIRCUIT ARCHITECTURE

Organization Name

QUALCOMM Incorporated

Inventor(s)

David Li of San Diego CA (US)

Rahul Biradar of Kalaburgi (IN)

Biju Manakkam Veetil of Bengaluru (IN)

Po-Hung Chen of Los Angeles CA (US)

Ayan Paul of San Diego CA (US)

Sung Son of San Jose CA (US)

Shivendra Kushwaha of Bangalore (IN)

Ravindra Reddy Chekkera of Vemula (IN)

Derek Yang of Poway CA (US)

MEMORY CIRCUIT ARCHITECTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18163146 titled 'MEMORY CIRCUIT ARCHITECTURE

Simplified Explanation

The patent application describes a semiconductor device that includes a memory circuit with multiple quadrants arranged at the corners of the circuit. These quadrants surround a bank control component.

• Each quadrant has a bit cell core and a set of input output circuits that can access the bit cell core.
• The first quadrant is defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit.
• The second quadrant is adjacent to the first quadrant, and the border between them forms a symmetrical axis.

Potential applications of this technology:

• Memory devices: This semiconductor device can be used in various memory devices, such as RAM (Random Access Memory) or flash memory.
• Data storage systems: The technology can be applied in data storage systems to enhance memory access and organization.

Problems solved by this technology:

• Efficient memory access: The arrangement of quadrants and input output circuits allows for efficient access to the memory cells, improving overall performance.
• Symmetrical design: The symmetrical axis between the quadrants ensures balanced access and operation, reducing potential bottlenecks.

Benefits of this technology:

• Improved performance: The design of the semiconductor device enables faster and more efficient memory access, leading to improved overall performance.
• Enhanced scalability: The quadrant arrangement allows for easy scalability of the memory circuit, making it adaptable to different memory requirements.

Original Abstract Submitted

A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.