18152176. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Po-Han Wang of Hsinchu City (TW)
Sih-Hao Liao of New Taipei City (TW)
Yu-Hsiang Hu of Hsinchu City (TW)
Hung-Jui Kuo of Hsinchu City (TW)
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18152176 titled 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Simplified Explanation
The semiconductor package described in the abstract includes a die, an underfill layer, a patterned dielectric layer, and conductive terminals. The die is encapsulated by the underfill layer, with the back surface of the die and the surface of the underfill layer being coplanar. The patterned dielectric layer is on the back surface of the die, and the conductive terminals are on the patterned dielectric layer, partially embedded in it, and in contact with the die.
- Die encapsulated by underfill layer
- Patterned dielectric layer on back surface of die
- Conductive terminals on patterned dielectric layer, in contact with die
- Surface of patterned dielectric layer under each terminal parallel to back surface of die
Potential Applications
The technology described in the patent application could be applied in various semiconductor packaging applications, such as in microprocessors, memory chips, and integrated circuits.
Problems Solved
This technology helps in improving the reliability and performance of semiconductor packages by ensuring proper encapsulation of the die, providing electrical connections through conductive terminals, and maintaining coplanarity between different layers.
Benefits
The benefits of this technology include enhanced reliability, improved electrical connections, better thermal management, and overall improved performance of semiconductor packages.
Potential Commercial Applications
The technology could find commercial applications in the semiconductor industry for manufacturing advanced and reliable semiconductor packages for various electronic devices.
Possible Prior Art
One possible prior art could be the use of underfill layers and conductive terminals in semiconductor packaging to provide electrical connections and protect the die. However, the specific configuration described in this patent application, with the coplanarity of layers and the patterned dielectric layer, may be a novel innovation.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of cost-effectiveness?
The article does not provide information on the cost-effectiveness of this technology compared to existing semiconductor packaging methods. Further research or data would be needed to determine the cost implications of implementing this technology.
What impact does this technology have on the overall size and weight of the semiconductor package?
The article does not address the impact of this technology on the size and weight of the semiconductor package. Additional information or testing would be required to assess any changes in size and weight resulting from the implementation of this technology.
Original Abstract Submitted
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.
