18145095. MESSAGE AUTHENTICATION GALOIS INTEGRITY AND CORRECTION (MAGIC) FOR LIGHTWEIGHT ROW HAMMER MITIGATION simplified abstract (Intel Corporation)
MESSAGE AUTHENTICATION GALOIS INTEGRITY AND CORRECTION (MAGIC) FOR LIGHTWEIGHT ROW HAMMER MITIGATION
Organization Name
Inventor(s)
Sergej Deutsch of Hillsboro OR (US)
Christoph Dobraunig of St. Veit an der Glan (AT)
Rajat Agarwal of Portland OR (US)
David M. Durham of Beaverton OR (US)
Santosh Ghosh of Hillsboro OR (US)
Karanvir Grewal of Hillsboro OR (US)
Krystian Matusiewicz of Gdansk (PL)
MESSAGE AUTHENTICATION GALOIS INTEGRITY AND CORRECTION (MAGIC) FOR LIGHTWEIGHT ROW HAMMER MITIGATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18145095 titled 'MESSAGE AUTHENTICATION GALOIS INTEGRITY AND CORRECTION (MAGIC) FOR LIGHTWEIGHT ROW HAMMER MITIGATION
Simplified Explanation
The technology described in this patent application involves the use of bijection diffusion function circuits to diffuse data bits and error correcting code (ECC) bits. These diffused bits are then stored in a memory.
- The technology uses a first set of bijection diffusion function circuits to diffuse data bits and store them in a memory.
- An error correcting code (ECC) generation circuit is used to generate ECC bits for the data bits.
- A second set of bijection diffusion function circuits is used to diffuse the ECC bits and store them in the memory.
Potential applications of this technology:
- Data storage systems
- Communication systems
- Error correction in digital systems
Problems solved by this technology:
- Data loss or corruption during storage or transmission
- Efficient error correction in digital systems
Benefits of this technology:
- Improved data reliability and integrity
- Enhanced error correction capabilities
- Efficient use of memory space
Original Abstract Submitted
The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.
