18068337. STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES
Organization Name
Inventor(s)
Joonsuc Jang of HWASEONG-SI (KR)
STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18068337 titled 'STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES
Simplified Explanation
The patent application describes a storage device that includes a nonvolatile memory device and a memory controller. The memory device has a memory cell array with different regions for normal cells, parity cells, and redundancy cells. The memory controller has an error correction code (ECC) engine to generate parity data.
- The storage device includes a nonvolatile memory device and a memory controller.
- The memory device has a memory cell array with normal cells, parity cells, and redundancy cells.
- First bit-lines are connected to the normal and parity cell regions, while second bit-lines are connected to the redundancy cell region.
- The memory controller has an ECC engine to generate parity data.
- User data is stored in the normal cell region.
- The memory controller performs column repair on defective bit-lines in the first region.
- Additional column addresses are assigned to the defective bit-lines and the second bit-lines.
- At least a portion of the parity data is stored in a region corresponding to the additionally assigned column addresses.
Potential Applications
- Data storage devices such as solid-state drives (SSDs) and flash memory cards.
- Computer systems and servers that require reliable and efficient storage.
Problems Solved
- Addressing and repairing defective bit-lines in a memory cell array.
- Ensuring data integrity and reliability in nonvolatile memory devices.
Benefits
- Improved data storage reliability and error correction capabilities.
- Efficient utilization of memory cell array by assigning additional column addresses.
- Enhanced performance and longevity of storage devices.
Original Abstract Submitted
A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
