18059124. MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICE
Organization Name
Inventor(s)
MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18059124 titled 'MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICE
Simplified Explanation
The patent application describes a memory device that includes a cell array, a peripheral circuit, and a test logic circuit. It also includes a first regulator that regulates a power supply voltage and a power manager that provides a test power supply voltage.
- The memory device includes a cell array, peripheral circuit, and test logic circuit.
- A first regulator regulates a power supply voltage received through a first pad and provides it to the cell array and peripheral circuit.
- A power manager is placed between the first pad and the first regulator, and between the first pad and the test logic circuit.
- The power manager provides a test power supply voltage to the test logic circuit.
- In the test mode, the first target voltage level of the first regulator fluctuates, while the second target voltage level of the power manager remains constant.
Potential applications of this technology:
- Memory devices in various electronic devices such as smartphones, tablets, and computers.
- Testing and debugging memory cells in the manufacturing process.
Problems solved by this technology:
- Fluctuations in the power supply voltage can affect the performance and reliability of memory cells.
- Maintaining a constant target voltage level in the power manager during testing ensures accurate and reliable test operations.
Benefits of this technology:
- Improved performance and reliability of memory cells.
- Accurate and reliable testing and debugging of memory cells during the manufacturing process.
Original Abstract Submitted
Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.
