18054225. SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER
Organization Name
Inventor(s)
Soohyun Nam of Hwaseong-si (KR)
Haejung Yu of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18054225 titled 'SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER
Simplified Explanation
The patent application describes a semiconductor package that includes an interposer with through-electrodes, stacked semiconductor chips, and a package molding layer.
- The interposer has a base layer and through-electrodes that penetrate it.
- The stacked structure includes a first semiconductor chip and multiple second semiconductor chips stacked on top of it.
- A chip molding layer is applied to the side surface of the second semiconductor chips.
- Additional third semiconductor chips are attached to the interposer next to the stacked structure.
- A package molding layer surrounds the stacked structure and the third semiconductor chips on the interposer.
Potential applications of this technology:
- Integrated circuits and electronic devices
- Semiconductor manufacturing industry
Problems solved by this technology:
- Improved packaging and integration of multiple semiconductor chips
- Enhanced electrical connectivity and performance
Benefits of this technology:
- Compact and efficient design
- Improved reliability and durability
- Enhanced electrical performance and connectivity
Original Abstract Submitted
A semiconductor package includes an interposer including a base layer and a plurality of interposer through-electrodes penetrating the base layer; at least one stacked structure attached to the interposer and including a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and a chip molding layer on a side surface of the plurality of second semiconductor chips; a plurality of third semiconductor chips attached to the interposer adjacent the at least one stacked structure; and a package molding layer extending around the at least one stacked structure and the plurality of third semiconductor chips on the interposer.
