18052644. MEMORY DEVICES AND METHODS FOR CONTROLLING ROW HAMMER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

MEMORY DEVICES AND METHODS FOR CONTROLLING ROW HAMMER

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Seongjin Cho of Hwaseong-si (KR)

MEMORY DEVICES AND METHODS FOR CONTROLLING ROW HAMMER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18052644 titled 'MEMORY DEVICES AND METHODS FOR CONTROLLING ROW HAMMER

Simplified Explanation

The patent application describes memory devices and methods for controlling a row hammer. Here are the key points:

• The memory device includes a memory cell array with a word line and multiple counter memory cells that store an access count value of the word line.
• A control logic circuit monitors a row address accessing the word line during a specific time frame and determines it as a row hammer address if the number of accesses to the word line exceeds a threshold value.
• The row hammer address is stored in an address storage.
• The control logic circuit delays the determination of the next row hammer address when the address storage is full, indicated by a latch full signal.

Potential applications of this technology:

• Memory devices in computers, smartphones, and other electronic devices.
• Data centers and cloud computing facilities that rely on high-performance memory systems.

Problems solved by this technology:

• Row hammer is a phenomenon where repeated accesses to a specific row in a memory cell array can cause bit flips in adjacent rows, leading to data corruption.
• This technology helps identify and control row hammer addresses, preventing potential data corruption and system instability.

Benefits of this technology:

• Efficient monitoring and control of row hammer addresses, reducing the risk of data corruption.
• Improved reliability and stability of memory systems.
• Enhanced performance and longevity of memory devices.

Original Abstract Submitted

Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.