18051142. STATIC RANDOM-ACCESS MEMORY (SRAM) APPARATUS AND METHOD FOR REDUCING WIRE DELAY simplified abstract (Samsung Electronics Co., Ltd.)
STATIC RANDOM-ACCESS MEMORY (SRAM) APPARATUS AND METHOD FOR REDUCING WIRE DELAY
Organization Name
Inventor(s)
Lava Kumar Pulluru of Bengaluru (IN)
Gopi Sunanth Kumar Gogineni of Bengaluru (IN)
Manish Chandra Joshi of Bengaluru (IN)
Pushp Khatter of Bengaluru (IN)
STATIC RANDOM-ACCESS MEMORY (SRAM) APPARATUS AND METHOD FOR REDUCING WIRE DELAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18051142 titled 'STATIC RANDOM-ACCESS MEMORY (SRAM) APPARATUS AND METHOD FOR REDUCING WIRE DELAY
Simplified Explanation
The abstract describes a SRAM apparatus with left and right memory arrays, each divided into segments with memory bit cells and connected to central driver circuitry for routing array signals.
- SRAM apparatus with left and right memory arrays
- Memory arrays divided into segments with memory bit cells
- Central driver circuitry with driver devices connected to segments through control lines
- Central driver circuitry routes array signals to segments
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- Potential Applications
- High-speed cache memory in computer systems
- Embedded memory in microcontrollers
- Buffer memory in networking devices
- Problems Solved
- Faster access times for memory operations
- Efficient routing of array signals to memory segments
- Improved reliability and performance of SRAM devices
- Benefits
- Increased speed and efficiency in memory operations
- Enhanced performance of computing devices
- Improved overall system reliability and responsiveness
Original Abstract Submitted
Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.
