18047954. OPTIMIZATION OF VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR INTEGRATION simplified abstract (QUALCOMM Incorporated)

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OPTIMIZATION OF VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR INTEGRATION

Organization Name

QUALCOMM Incorporated

Inventor(s)

Xia Li of San Diego CA (US)

Bin Yang of San Diego CA (US)

Haining Yang of San Diego CA (US)

OPTIMIZATION OF VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR INTEGRATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18047954 titled 'OPTIMIZATION OF VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR INTEGRATION

Simplified Explanation

The abstract describes a vertical transport field effect transistor (VTFET) with multiple FET structures on a substrate, including n-type and p-type FET structures oriented in different directions. Each structure has a FIN with a defined height, allowing for charge carriers to be transported along the FIN height.

  • The VTFET comprises multiple FET structures on a substrate.
  • The FET structures include n-type and p-type FET structures oriented in different directions.
  • Each structure has a FIN with a defined height for transporting charge carriers along the FIN height.

Potential Applications

The technology could be applied in:

  • High-speed electronic devices
  • Power amplifiers
  • Signal processing circuits

Problems Solved

  • Improved charge carrier transport efficiency
  • Enhanced performance of vertical transport field effect transistors

Benefits

  • Increased speed and efficiency in electronic devices
  • Better power management capabilities
  • Enhanced signal processing performance

Potential Commercial Applications

Optimizing Vertical Transport Field Effect Transistors for Improved Electronic Devices

Possible Prior Art

One possible prior art could be the use of traditional field effect transistors with horizontal charge carrier transport mechanisms.

Unanswered Questions

How does the FIN height impact the overall performance of the VTFET?

The abstract mentions the FIN height as a key parameter, but it does not elaborate on its specific effects on the transistor's performance.

Are there any limitations to the charge carrier transport along the FIN height?

While the abstract highlights the ability of the FIN to transport charge carriers, it does not address any potential limitations or challenges in this process.


Original Abstract Submitted

A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.