18045971. MEMORY DEVICE HAVING VERTICAL STRUCTURE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MEMORY DEVICE HAVING VERTICAL STRUCTURE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
Organization Name
Inventor(s)
Sunghoon Kim of SEONGNAM-SI (KR)
Daeseok Byeon of SEONGNAM-SI (KR)
MEMORY DEVICE HAVING VERTICAL STRUCTURE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18045971 titled 'MEMORY DEVICE HAVING VERTICAL STRUCTURE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
Simplified Explanation
The patent application describes a memory device that consists of multiple semiconductor layers.
- The first lower semiconductor layer is located below a first upper semiconductor layer, which contains a memory cell array.
- The first lower semiconductor layer includes a first page buffer that is electrically connected to the memory cell array.
- The second lower semiconductor layer is positioned below a second upper semiconductor layer, which also contains a memory cell array.
- The second lower semiconductor layer is adjacent to the first upper semiconductor layer in a specific direction.
- The second lower semiconductor layer includes a first portion of a second page buffer that is electrically connected to the second memory cell array.
- The first lower semiconductor layer also includes a second portion of the second page buffer, which is different from the first portion.
Potential applications of this technology:
- Memory devices in various electronic devices such as smartphones, tablets, and computers.
- Storage devices in data centers and servers.
Problems solved by this technology:
- Efficient utilization of space in memory devices by stacking multiple semiconductor layers.
- Improved performance and data transfer speed by utilizing separate page buffers for different memory cell arrays.
Benefits of this technology:
- Increased memory capacity in a compact form factor.
- Enhanced data processing and storage capabilities.
- Improved overall performance and efficiency of electronic devices.
Original Abstract Submitted
A memory device includes a first lower semiconductor layer and a second lower semiconductor layer. The first lower semiconductor layer is disposed below a first upper semiconductor layer including a first memory cell array. The first lower semiconductor layer includes a first page buffer electrically connected to the first memory cell array. The second lower semiconductor layer is disposed below a second upper semiconductor layer includes a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction. The second lower semiconductor layer includes a first portion of a second page buffer electrically connected to the second memory cell array and being disposed adjacent to the first lower semiconductor layer in the first direction. The first lower semiconductor layer further includes a second portion of the second page buffer different from the first portion.
