17966993. COMPUTER-IMPLEMENTED METHOD AND COMPUTING SYSTEM FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING TIMING DELAY simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 COMPUTER-IMPLEMENTED METHOD AND COMPUTING SYSTEM FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING TIMING DELAY
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 COMPUTER-IMPLEMENTED METHOD AND COMPUTING SYSTEM FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING TIMING DELAY - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
COMPUTER-IMPLEMENTED METHOD AND COMPUTING SYSTEM FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING TIMING DELAY
Organization Name
Inventor(s)
Bong-il Park of Seongnam-si (KR)
Sun-ik Heo of Hwaseong-si (KR)
COMPUTER-IMPLEMENTED METHOD AND COMPUTING SYSTEM FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING TIMING DELAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17966993 titled 'COMPUTER-IMPLEMENTED METHOD AND COMPUTING SYSTEM FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING TIMING DELAY
Simplified Explanation
The abstract describes a computer program code stored in a computer-readable storage medium that, when executed, enables the design of an integrated circuit (IC). The program includes tools such as a placing and routing tool and a timing analysis tool.
- The placing and routing tool generates layout data and wire data for a net in the IC.
- The wire data includes physical information about the wire used to implement the net.
- The timing analysis tool calculates the wire delay based on the physical information and updates it considering process variation.
- The tool then calculates the timing slack using the updated wire delay.
Potential Applications
- Integrated circuit design
- Semiconductor industry
- Electronics manufacturing
Problems Solved
- Efficient and accurate placement and routing of standard cells in an integrated circuit.
- Calculation of wire delay and timing slack considering process variation.
Benefits
- Improved efficiency and accuracy in designing integrated circuits.
- Better understanding of wire delay and timing slack, leading to optimized circuit performance.
- Reduction in design iterations and time-to-market for integrated circuits.
Original Abstract Submitted
A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.
