17964549. GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA simplified abstract (Intel Corporation)

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GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA

Organization Name

Intel Corporation

Inventor(s)

Jason M. Fung of Portland OR (US)

Debayan Das of Hillsboro OR (US)

Sayak Ray of San Jose CA (US)

Rana Elnaggar of San Jose CA (US)

Majid Sabbagh of Santa Clara CA (US)

GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA - A simplified explanation of the abstract

This abstract first appeared for US patent application 17964549 titled 'GENERIC SYNTHESIZABLE CIRCUIT COUNTERMEASURE AGAINST HARDWARE SCA

Simplified Explanation

The patent application describes an apparatus, system, and method for protecting a component from an observation attack using a power balancing circuit.

  • The power balancing circuit includes a ring oscillator connected to a power supply.
  • A time-to-digital converter (TDC) monitors an electrical parameter of the power drawn by the component and provides data indicating the parameter.
  • A controller circuit adjusts the number of inverters of the ring oscillator drawing power from the supply based on the data.

Potential Applications

This technology could be applied in secure communication systems, IoT devices, and other applications where protecting components from observation attacks is crucial.

Problems Solved

This technology addresses the issue of protecting sensitive components from observation attacks that could compromise security and privacy.

Benefits

The power balancing circuit provides a proactive defense mechanism against observation attacks, enhancing the overall security of the system.

Potential Commercial Applications

The technology could be valuable in industries such as cybersecurity, data encryption, and secure hardware development.

Possible Prior Art

One possible prior art could be the use of power analysis attacks in cryptography to extract secret keys from devices. This technology aims to mitigate such attacks by balancing power consumption.

Unanswered Questions

How does the power balancing circuit impact the overall performance of the protected component?

The article does not delve into the potential performance implications of implementing the power balancing circuit. It would be interesting to know if there are any trade-offs in terms of speed or efficiency.

Are there any limitations to the effectiveness of the power balancing circuit in protecting against observation attacks?

The article does not discuss any potential limitations or vulnerabilities of the power balancing circuit. It would be important to understand if there are any scenarios where this technology may not be as effective.


Original Abstract Submitted

An apparatus, system, and method for protecting a component from an observation attack are provided. A power balancing circuit configured to protect a cryptography component can include a ring oscillator electrically connected to a power supply, a time-to-digital converter (TDC) electrically connected to monitor an electrical parameter of the electrical power drawn by the cryptography component and provide data indicative of the electrical parameter, and a controller circuit configured to adjust a number of inverters of the ring oscillator drawing power from the power supply based on the data.