17962387. METHOD FOR POWER REDUCTION IN MEMORY MODULES simplified abstract (Dell Products L.P.)
Contents
- 1 METHOD FOR POWER REDUCTION IN MEMORY MODULES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD FOR POWER REDUCTION IN MEMORY MODULES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
METHOD FOR POWER REDUCTION IN MEMORY MODULES
Organization Name
Inventor(s)
Isaac Q. Wang of Austin TX (US)
Lee B. Zaretsky of Pflugerville TX (US)
METHOD FOR POWER REDUCTION IN MEMORY MODULES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17962387 titled 'METHOD FOR POWER REDUCTION IN MEMORY MODULES
Simplified Explanation
The clock buffer device for a memory module described in the abstract includes two phase-locked loops (PLLs) that can be selectively coupled to clock output buffers based on the configuration of the information handling system. When the first PLL receives a clock signal but the second PLL does not, the device disables the second PLL and connects the output of the first PLL to the clock output buffers.
- The clock buffer device includes two PLLs that can be selectively coupled to clock output buffers.
- The device can detect the configuration of the information handling system to determine which PLL to enable.
- When the first PLL receives a clock signal but the second PLL does not, the device disables the second PLL and connects the output of the first PLL to the clock output buffers.
Potential Applications
This technology can be applied in various memory modules and systems where precise clock signals are required for synchronization and data processing.
Problems Solved
1. Ensures accurate clock signal distribution within a memory module. 2. Allows for flexible configuration based on the requirements of the information handling system.
Benefits
1. Improved reliability and performance of memory modules. 2. Simplified clock signal management. 3. Enhanced system flexibility and adaptability.
Potential Commercial Applications
Optimizing clock signal distribution in servers, data centers, and other high-performance computing systems.
Possible Prior Art
Prior art related to clock buffer devices and PLLs in memory modules may exist, but specific examples are not provided in this abstract.
Unanswered Questions
=== How does the device handle potential signal interference or noise in the clock signals? The abstract does not mention how the device addresses signal interference or noise that could affect the accuracy of the clock signals.
=== What are the power consumption implications of using this clock buffer device? The abstract does not provide information on the power consumption of the device and how it may impact the overall energy efficiency of the system.
Original Abstract Submitted
A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.
