17957931. BURIED TRENCH CAPACITOR simplified abstract (TEXAS INSTRUMENTS INCORPORATED)

BURIED TRENCH CAPACITOR

Organization Name

TEXAS INSTRUMENTS INCORPORATED

Inventor(s)

Umamaheswari Aghoram of Richardson TX (US)

Guruvayurappan Mathur of Allen TX (US)

Robert Oppen of Phoenix AZ (US)

Tawen Mei of Sunnyvale CA (US)

BURIED TRENCH CAPACITOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 17957931 titled 'BURIED TRENCH CAPACITOR

Simplified Explanation

The microelectronic device described in the patent application includes a buried trench capacitor below an electronic component. The capacitor is formed between different regions separated by a dielectric layer, with terminals connected through substrate and well contacts.

• The buried trench capacitor is formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region.
• The terminals of the capacitor are connected through a deep trench substrate contact and a well contact, providing electrical connection to the capacitor.

Potential Applications

This technology could be applied in the manufacturing of advanced microelectronic devices, such as memory chips and processors, where high-density capacitors are required for efficient operation.

Problems Solved

This technology solves the problem of integrating high-capacity capacitors in microelectronic devices without increasing the overall size of the device, allowing for more efficient and compact designs.

Benefits

The benefits of this technology include increased capacitance in a smaller footprint, improved performance of microelectronic devices, and potentially lower power consumption due to more efficient capacitor design.

Potential Commercial Applications

This technology could be commercially applied in the semiconductor industry for the production of high-performance memory modules, processors, and other advanced electronic devices.

Possible Prior Art

One possible prior art for this technology could be the use of buried trench capacitors in microelectronic devices, but the specific configuration and connection methods described in this patent application may be novel and inventive.

How does this technology compare to traditional capacitor designs in terms of performance and efficiency?

This article does not provide a direct comparison between this technology and traditional capacitor designs in terms of performance metrics such as capacitance, leakage current, or size efficiency.

What are the potential challenges in implementing this technology in large-scale production processes?

This article does not address the potential challenges or limitations in scaling up the production of microelectronic devices using this technology, such as manufacturing costs, yield rates, or compatibility with existing fabrication processes.

Original Abstract Submitted

A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.