17957875. FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
Contents
- 1 FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does the specific lateral distance between the conductive field deflector and the lower winding affect the performance of the galvanic isolation component?
- 1.11 What are the potential challenges in integrating this technology into existing electronic systems?
- 1.12 Original Abstract Submitted
FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Jeffrey Alan West of Dallas TX (US)
Byron Lovell Williams of Plano TX (US)
Kashyap Barot of Bangalore (IN)
Sreeram N. S. of Bangalore (IN)
Viresh Chinchansure of Bangalore (IN)
FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17957875 titled 'FIELD SUPPRESSION FEATURE FOR GALVANIC ISOLATION DEVICE
Simplified Explanation
The microelectronic device described in the patent application includes a galvanic isolation component with a lower winding, an upper isolation element, and a field suppression structure. The field suppression structure contains a conductive field deflector that is positioned a specific distance away from the lower winding, and is electrically connected to a semiconductor material in a substrate.
- The galvanic isolation component consists of a lower winding and an upper isolation element with a field suppression structure.
- The field suppression structure includes a conductive field deflector separated from the lower winding by a specific lateral distance.
- The conductive field deflector is electrically connected to a semiconductor material in a substrate.
- The lower winding is separated from the substrate by a first dielectric layer, while the upper isolation element is separated from the lower winding by a second dielectric layer.
Potential Applications
The technology described in this patent application could be used in various electronic devices that require galvanic isolation, such as power supplies, motor drives, and communication systems.
Problems Solved
This technology helps to provide galvanic isolation in microelectronic devices, which is essential for preventing electrical interference and ensuring safety in electronic systems.
Benefits
The benefits of this technology include improved performance, increased safety, and reduced electromagnetic interference in electronic devices.
Potential Commercial Applications
This technology could be commercially applied in industries such as telecommunications, automotive, industrial automation, and consumer electronics.
Possible Prior Art
One possible prior art for this technology could be existing galvanic isolation components used in electronic devices, but with different configurations or materials.
Unanswered Questions
How does the specific lateral distance between the conductive field deflector and the lower winding affect the performance of the galvanic isolation component?
The specific distance between the conductive field deflector and the lower winding could impact the efficiency of the galvanic isolation and the overall performance of the microelectronic device.
What are the potential challenges in integrating this technology into existing electronic systems?
Integrating this technology into existing electronic systems may pose challenges related to compatibility, size constraints, and manufacturing processes.
Original Abstract Submitted
A microelectronic device includes a galvanic isolation component. The galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. The galvanic isolation component further includes a field suppression structure located interior to the lower winding. The field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. A top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. The conductive field deflector is electrically connected to a semiconductor material in a substrate. The lower winding is separated from a substrate by a first dielectric layer. The upper isolation element is separated from the lower winding by a second dielectric layer.
