17955653. AUTOMATED VERIFICATION OF TECHNOLOGY SPECIFIC AND TECHNOLOGY INDEPENDENT LOGIC MODELS OF A MEMORY ARRAY simplified abstract (International Business Machines Corporation)

AUTOMATED VERIFICATION OF TECHNOLOGY SPECIFIC AND TECHNOLOGY INDEPENDENT LOGIC MODELS OF A MEMORY ARRAY

Organization Name

International Business Machines Corporation

Inventor(s)

Thomas Kalla of Boeblingen (DE)

Jentje Leenstra of Bondorf (DE)

Richard Louis Henry Carbone of Webster NY (US)

Philipp Salz of Altdorf (DE)

AUTOMATED VERIFICATION OF TECHNOLOGY SPECIFIC AND TECHNOLOGY INDEPENDENT LOGIC MODELS OF A MEMORY ARRAY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17955653 titled 'AUTOMATED VERIFICATION OF TECHNOLOGY SPECIFIC AND TECHNOLOGY INDEPENDENT LOGIC MODELS OF A MEMORY ARRAY

Simplified Explanation

The abstract describes a computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array. The method involves creating sets of parameters and constraints, generating the technology independent model using the second set of parameters and constraints, generating the technology specific model using the first set of parameters and constraints, and verifying the equivalence of both models on a sequential logic basis.

• Explanation of the patent/innovation:

- Automated method for creating and verifying logic models of memory arrays - Utilizes sets of parameters and constraints to generate technology specific and independent models - Verifies equivalence of the models based on sequential logic

Potential applications of this technology

- Semiconductor industry for memory array design - Computer hardware development for optimizing memory performance

Problems solved by this technology

- Streamlining the process of generating logic models for memory arrays - Ensuring accuracy and consistency in technology specific and independent models

Benefits of this technology

- Increased efficiency in memory array design - Reduction in manual errors and inconsistencies - Enhanced verification process for logic models

Possible prior art

There may be existing methods or tools for generating logic models of memory arrays, but the specific automated process described in this patent application may be novel and innovative.

How does this method compare to manual generation of logic models for memory arrays?

This article does not provide a direct comparison between the automated method and manual generation of logic models. It would be interesting to know the time and resource savings, as well as the accuracy and consistency improvements, achieved by using this automated approach.

What are the potential limitations or challenges in implementing this automated method in real-world memory array design processes?

The article does not address any potential limitations or challenges that may arise when implementing this automated method. It would be important to consider factors such as compatibility with existing design tools, learning curve for users, and adaptability to different memory array configurations.

Original Abstract Submitted

A computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array, the method at least comprising: having a first set of parameters; having a set of constraints, creating a second set of parameters; generating the technology independent model of the memory array wherein the second set of parameters and the set of constraints are used; generating the technology specific model of the memory array wherein the first set of parameters and the set of constraints are used; verifying the technology independent model and the technology specific model for equivalence on a sequential logic basis.