17950375. LAYOUT CHECK SYSTEM USING FULL-CHIP LAYOUT AND LAYOUT CHECK METHOD USING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
LAYOUT CHECK SYSTEM USING FULL-CHIP LAYOUT AND LAYOUT CHECK METHOD USING THE SAME
Organization Name
Inventor(s)
Kyungmi Yeom of Yongin-si (KR)
Alexander Shmidt of Suwon-si (KR)
Anthony Pierre Gerard Payet of Seongnam-si (KR)
LAYOUT CHECK SYSTEM USING FULL-CHIP LAYOUT AND LAYOUT CHECK METHOD USING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17950375 titled 'LAYOUT CHECK SYSTEM USING FULL-CHIP LAYOUT AND LAYOUT CHECK METHOD USING THE SAME
Simplified Explanation
The abstract describes a method for checking the layout of a chip design by generating a layout shell structure and a process condition model. The method involves performing stress simulations and extracting statistics data based on the simulation results. The layout shell structure and process condition model are configured to have dimensions between two and three.
- The method involves preprocessing a full-chip layout to generate a layout shell structure.
- At least one process condition is preprocessed to generate a process condition model.
- Stress simulations are performed on the layout shell structure and process condition model.
- The stress simulation value of the layout shell structure is extracted.
- Statistics data is extracted based on the stress simulation value.
- The layout shell structure and process condition model have dimensions between two and three.
Potential Applications
- This method can be used in the semiconductor industry for layout verification of chip designs.
- It can help identify potential issues and optimize the layout for better performance.
Problems Solved
- The method solves the problem of efficiently checking the layout of a chip design.
- It helps identify potential stress-related issues in the layout.
- By extracting statistics data, it provides insights into the performance of the layout.
Benefits
- The method allows for a more comprehensive layout check by considering both the layout shell structure and process conditions.
- It helps improve the reliability and performance of chip designs.
- By extracting statistics data, it enables designers to make informed decisions for layout optimization.
Original Abstract Submitted
A layout check method includes generating a layout shell structure by preprocessing a full-chip layout, generating a process condition model by preprocessing at least one process condition, extracting a stress simulation value of the layout shell structure by performing a stress simulation based on the layout shell structure and on the process condition model, and extracting statistics data based on the stress simulation value of the layout shell structure, wherein the layout shell structure and the process condition model are configured to have a dimension which is greater than two dimensions and less than three dimensions.
