17949803. HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS simplified abstract (Intel Corporation)

HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS

Organization Name

Intel Corporation

Inventor(s)

Mark Dechene of Hillsboro OR (US)

Ryan Carlson of Hillsboro OR (US)

Sudeepto Majumdar of Hillsboro OR (US)

Rafael Trapani Possignolo of Hillsboro OR (US)

Paula Petrica of Portland OR (US)

Richard Klass of Hillsboro OR (US)

Meenakshi Marathe of Hillsboro OR (US)

HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17949803 titled 'HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS

Simplified Explanation

The patent application describes techniques for slicing memory of a hardware processor core by linear address. The hardware processor core includes memory circuitry with a cache comprising multiple slices of memory, each storing a different range of address values compared to any other slice. Each slice includes an incomplete load buffer, a store address buffer, a store data buffer, and a store completion buffer.

• Incomplete load buffer to store load address for a load request operation
• Store address buffer to store store address for a store request operation
• Store data buffer to store data for each store request operation
• Store completion buffer to store data for the store request operation and clear the store address and data buffers

Potential Applications

This technology could be applied in high-performance computing systems, embedded systems, and networking devices.

Problems Solved

This technology helps in efficiently managing memory access requests and improving the overall performance of the hardware processor core.

Benefits

The benefits of this technology include faster memory access, reduced latency, and optimized memory utilization in hardware processor cores.

Potential Commercial Applications

The potential commercial applications of this technology include data centers, cloud computing infrastructure, and IoT devices.

Possible Prior Art

One possible prior art could be the use of multi-level cache systems in hardware processor cores to improve memory access performance.

What are the specific ranges of address values stored in each slice of memory?

The specific ranges of address values stored in each slice of memory are not provided in the abstract.

How does this technology compare to existing memory slicing techniques in terms of efficiency and performance?

The abstract does not provide a direct comparison of this technology to existing memory slicing techniques in terms of efficiency and performance.

Original Abstract Submitted

Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.