17947672. APPARATUS AND METHODS FOR BONDING PAD REDISTRIBUTION LAYERS IN INTEGRATED CIRCUITS simplified abstract (SanDisk Technologies LLC)

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APPARATUS AND METHODS FOR BONDING PAD REDISTRIBUTION LAYERS IN INTEGRATED CIRCUITS

Organization Name

SanDisk Technologies LLC

Inventor(s)

Guangyuan Li of Santa Clara CA (US)

Yuji Totoki of Milpitas CA (US)

Fumiaki Toyama of Cupertino CA (US)

APPARATUS AND METHODS FOR BONDING PAD REDISTRIBUTION LAYERS IN INTEGRATED CIRCUITS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17947672 titled 'APPARATUS AND METHODS FOR BONDING PAD REDISTRIBUTION LAYERS IN INTEGRATED CIRCUITS

Simplified Explanation

The patent application describes an apparatus with an integrated circuit die that includes multiple bonding pads on different metal layers, connected by conductors.

  • Integrated circuit die with uppermost metal layer
  • Plurality of first bonding pads on uppermost metal layer
  • First additional metal layer above uppermost metal layer
  • Plurality of second bonding pads on first additional metal layer
  • Conductors connecting first bonding pads to second bonding pads

Potential Applications

The technology described in the patent application could be used in various electronic devices such as smartphones, tablets, and computers.

Problems Solved

This technology allows for more efficient and compact integration of components in electronic devices, improving overall performance and functionality.

Benefits

- Improved electrical connectivity - Enhanced circuit integration - Increased device performance

Potential Commercial Applications

Optimizing Bonding Pad Connectivity in Integrated Circuits for Enhanced Electronic Devices

Possible Prior Art

There may be prior art related to the integration of multiple metal layers in integrated circuit dies for improved connectivity and performance.

Unanswered Questions

How does this technology impact the overall size of electronic devices?

The patent application does not provide specific details on how the integration of multiple metal layers affects the size of electronic devices.

What are the potential challenges in manufacturing integrated circuits with multiple metal layers?

The patent application does not address any potential challenges that may arise during the manufacturing process of integrated circuits with multiple metal layers.


Original Abstract Submitted

An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.