View source for 17937313. POWER VIA WITH REDUCED RESISTANCE simplified abstract (ATI TECHNOLOGIES ULC)

=POWER VIA WITH REDUCED RESISTANCE=


==Organization Name==

[[:Category:ATI TECHNOLOGIES ULC|ATI TECHNOLOGIES ULC]]


[[Category:ATI TECHNOLOGIES ULC]]

==Inventor(s)==

[[:Category:Richard T. Schultz of Fort Collins CO (US)|Richard T. Schultz of Fort Collins CO (US)]][[Category:Richard T. Schultz of Fort Collins CO (US)]]

[[:Category:Omid Rowhani of Markham (CA)|Omid Rowhani of Markham (CA)]][[Category:Omid Rowhani of Markham (CA)]]

==POWER VIA WITH REDUCED RESISTANCE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17937313 titled 'POWER VIA WITH REDUCED RESISTANCE

==Simplified Explanation==

The patent application describes an apparatus and method for efficiently routing power signals across a semiconductor die. The integrated circuit includes micro through silicon vias (TSVs) that traverse through a silicon substrate layer to a backside metal layer, providing power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.

* Integrated circuit includes micro TSVs that traverse through silicon substrate layer to backside metal layer
* First node receives power supply reference, connected to first micro TSV
* Second node receives power supply reference, connected to second micro TSV
* First power rail connects first micro TSV to second micro TSV, replacing contacts between micro TSVs and frontside metal zero (M0) layer
* Power connection redundancy provided by first power rail, second power rail, and backside metal layer

== Potential Applications ==
This technology can be applied in the semiconductor industry for efficient power signal routing in integrated circuits, improving charge sharing and reducing voltage droop.

== Problems Solved ==
This technology solves the problem of inefficient power signal routing across a semiconductor die, increasing charge sharing, improving wafer yield, and reducing voltage droop.

== Benefits ==
The benefits of this technology include increased efficiency in power signal routing, improved charge sharing, enhanced wafer yield, and reduced voltage droop in integrated circuits.

== Potential Commercial Applications ==
This technology can be commercially applied in the semiconductor industry for manufacturing more efficient and reliable integrated circuits with improved power signal routing capabilities.

== Possible Prior Art ==
One possible prior art could be the use of traditional power signal routing methods in integrated circuits, which may not provide the same level of power connection redundancy and efficiency as the described apparatus and method.

=== Unanswered Questions ===

=== How does this technology compare to existing power signal routing methods in terms of efficiency and reliability? ===
This article does not directly compare the efficiency and reliability of this technology to existing power signal routing methods. 

=== What are the potential challenges in implementing this technology on a large scale in semiconductor manufacturing processes? ===
This article does not address the potential challenges in implementing this technology on a large scale in semiconductor manufacturing processes.


==Original Abstract Submitted==

An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.



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