17933327. SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS simplified abstract (QUALCOMM Incorporated)

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SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS

Organization Name

QUALCOMM Incorporated

Inventor(s)

Jianjun Yu of San Diego CA (US)

Tomas O'sullivan of San Diego CA (US)

Razak Hossain of San Diego CA (US)

Lai Kan Leung of San Marcos CA (US)

SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17933327 titled 'SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS

Simplified Explanation

The abstract of the patent application describes techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. The method involves performing a synchronizing action at two PLL circuits in response to obtaining an indication to do so.

  • Synchronizing action performed at first and second PLL circuits
  • Response to obtaining indication to synchronize
  • Techniques and apparatus for PLL circuit synchronization

Potential Applications

The technology can be applied in various fields where precise synchronization of PLL circuits is required, such as:

  • Telecommunications
  • Radar systems
  • Satellite communication
  • Wireless networks

Problems Solved

The technology addresses the following issues:

  • Ensuring accurate synchronization between PLL circuits
  • Minimizing phase differences
  • Improving overall system performance

Benefits

The benefits of this technology include:

  • Enhanced system reliability
  • Improved signal accuracy
  • Reduced interference
  • Increased data transmission efficiency

Potential Commercial Applications

The technology has potential commercial applications in industries such as:

  • Telecommunications equipment manufacturing
  • Aerospace and defense technology
  • Networking hardware development
  • Semiconductor industry

Possible Prior Art

One possible prior art related to this technology could be the use of traditional synchronization methods in PLL circuits, which may not be as efficient or accurate as the techniques described in the patent application.

Unanswered Questions

How does the technology handle variations in operating conditions that may affect PLL circuit synchronization?

The article does not delve into how the technology adapts to changing environments or conditions that could impact the synchronization process.

Are there any limitations to the scalability of this technology for large-scale systems?

The scalability of the technology for applications involving a high number of PLL circuits or complex systems is not discussed in detail in the article.


Original Abstract Submitted

Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit; and performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication.