17932572. ALIAS REJECTION IN ANALOG-TO-DIGITAL CONVERTERS (ADCs) simplified abstract (QUALCOMM Incorporated)
Contents
- 1 ALIAS REJECTION IN ANALOG-TO-DIGITAL CONVERTERS (ADCs)
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ALIAS REJECTION IN ANALOG-TO-DIGITAL CONVERTERS (ADCs) - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
ALIAS REJECTION IN ANALOG-TO-DIGITAL CONVERTERS (ADCs)
Organization Name
Inventor(s)
Behnam Sedighi of La Jolla CA (US)
ALIAS REJECTION IN ANALOG-TO-DIGITAL CONVERTERS (ADCs) - A simplified explanation of the abstract
This abstract first appeared for US patent application 17932572 titled 'ALIAS REJECTION IN ANALOG-TO-DIGITAL CONVERTERS (ADCs)
Simplified Explanation
The patent application describes techniques and apparatus for alias rejection in analog-to-digital converters (ADCs) by operating only a portion of the ADC at a higher sampling rate than other portions, preventing aliasing while saving power.
- A first circuit portion operates at a clock rate equal to the ADC's sampling rate.
- A second circuit portion operates at a higher clock rate than the sampling rate of the ADC.
Potential Applications
This technology can be applied in various fields such as telecommunications, medical imaging, radar systems, and audio processing where high-quality signal conversion is required.
Problems Solved
1. Prevents aliasing in ADCs, ensuring accurate signal conversion. 2. Saves power by operating only a portion of the ADC at a higher sampling rate.
Benefits
1. Improved signal quality and accuracy. 2. Reduced power consumption. 3. Cost-effective solution for high-performance ADCs.
Potential Commercial Applications
Optimizing Power Consumption in Analog-to-Digital Converters for Enhanced Signal Conversion
Possible Prior Art
One possible prior art is the use of oversampling techniques in ADCs to improve resolution and reduce noise. However, the specific approach of operating only a portion of the ADC at a higher sampling rate to prevent aliasing while saving power may be a novel innovation.
Unanswered Questions
How does this technology compare to existing oversampling techniques in terms of performance and power consumption?
This article does not provide a direct comparison between this technology and traditional oversampling techniques in terms of performance and power consumption.
Are there any limitations or drawbacks to implementing this technology in practical applications?
The article does not address any potential limitations or drawbacks that may arise from implementing this technology in real-world applications.
Original Abstract Submitted
Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.
