17899111. BACKSIDE CONTACTS FOR CELL HEIGHT SCALING simplified abstract (International Business Machines Corporation)
Contents
BACKSIDE CONTACTS FOR CELL HEIGHT SCALING
Organization Name
International Business Machines Corporation
Inventor(s)
Ruilong Xie of Niskayuna NY (US)
Chanro Park of Clifton Park NY (US)
Kangguo Cheng of Schenectady NY (US)
Julien Frougier of Albany NY (US)
Lawrence A. Clevenger of Saratoga Springs NY (US)
BACKSIDE CONTACTS FOR CELL HEIGHT SCALING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899111 titled 'BACKSIDE CONTACTS FOR CELL HEIGHT SCALING
Simplified Explanation
The semiconductor structure described in the patent application includes:
- A first dielectric isolation pillar between a pair of p-type field effect transistors (pFETs)
- A second dielectric isolation pillar between a pair of n-type FETs (nFETs)
- A first source/drain (S/D) epi region with a first contact connected to a backside power delivery network (BSPDN)
- The first contact is located on one side of the first dielectric isolation pillar
- A second S/D epi region with a second contact connected to back-end-of-line (BEOL) components
- The second contact is located on the other side of the first dielectric isolation pillar
Potential applications of this technology:
- Semiconductor manufacturing
- Integrated circuit design
- Power delivery networks
Problems solved by this technology:
- Improved isolation between different types of transistors
- Efficient power delivery and connection to back-end components
Benefits of this technology:
- Enhanced performance of field effect transistors
- Better power management in semiconductor devices
- Increased reliability and functionality of integrated circuits
Original Abstract Submitted
A semiconductor structure is presented including a first dielectric isolation pillar disposed between a pair of p-type field effect transistors (pFETs), a second dielectric isolation pillar disposed between a pair of n-type FETs (nFETs), a first source/drain (S/D) epi region having a first contact electrically connected to a backside power delivery network (BSPDN), the first contact being disposed on one side of the first dielectric isolation pillar, and a second S/D epi region having a second contact electrically connected to back-end-of-line (BEOL) components, the second contact being disposed on the other side of the first dielectric isolation pillar.