17878431. LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE
Organization Name
Inventor(s)
Geunyeong Yu of Seongnam-si (KR)
Youngjun Hwang of Osan-si (KR)
LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17878431 titled 'LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE
Simplified Explanation
The abstract describes a low density parity check (LDPC) decoder that uses an irregular parity check matrix to decode messages. The decoder has two modes: a single mode where all unit logic circuits update one variable node group, and a multi-mode where each unit logic circuit updates multiple variable node groups in parallel.
- The LDPC decoder initializes variable nodes with a codeword and outputs updated variable nodes as decoded messages.
- The decoder uses an irregular parity check matrix to perform the decoding process.
- The decoder has a mode controller that determines which mode (single or multi) the unit logic circuits operate in.
- In the single mode, all unit logic circuits update a high-degree variable node group, which has a degree greater than a threshold degree.
- In the multi-mode, each unit logic circuit updates a low-degree variable node group, which has a degree less than or equal to the threshold degree.
Potential Applications
- Error correction in communication systems: The LDPC decoder can be used to decode messages in communication systems, ensuring accurate transmission of data.
- Data storage: The decoder can be applied in storage systems to recover data from corrupted or damaged storage devices.
Problems Solved
- Efficient decoding: The LDPC decoder provides a method for decoding messages using an irregular parity check matrix, improving the efficiency of the decoding process.
- Handling variable node groups: The decoder addresses the challenge of updating variable node groups with different degrees, optimizing the decoding process for both high-degree and low-degree variable node groups.
Benefits
- Improved decoding performance: The LDPC decoder enhances the accuracy and reliability of decoding messages, leading to improved overall system performance.
- Flexibility in decoding modes: The decoder offers the flexibility to operate in either single or multi-mode, allowing for efficient decoding of variable node groups with different degrees.
Original Abstract Submitted
A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
