17873990. SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Juhyeon Kim of Cheonan-si (KR)
Youngkun Jee of Cheonan-si (KR)
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17873990 titled 'SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that includes two semiconductor chips stacked on top of each other. The first chip has a flat outer surface provided by a bonding layer, and the second chip is placed on top of the first chip, also with a flat outer surface provided by a bonding layer.
- The first semiconductor chip has a first substrate and a first bonding layer on top, which gives it a flat outer surface.
- The second semiconductor chip is placed on top of the first chip and has a second substrate and a second bonding layer on top, which also gives it a flat outer surface.
- The first bonding layer includes an outermost insulating layer, an internal insulating layer, external marks, and internal marks.
- The external marks are spaced apart on the outermost insulating layer, and the internal marks are interlaced with the external marks within the internal insulating layer.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- Integrated circuits for automotive applications.
- High-performance computing systems.
Problems solved by this technology:
- Provides a flat outer surface for semiconductor chips, allowing for better stacking and integration.
- Helps to reduce the size and thickness of semiconductor packages.
- Improves the electrical performance and reliability of the semiconductor package.
Benefits of this technology:
- Enables higher-density packaging of semiconductor chips.
- Enhances thermal management and heat dissipation.
- Improves signal integrity and reduces noise interference.
- Increases overall performance and functionality of electronic devices.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.
