17872143. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
Organization Name
Inventor(s)
SEOKHAN Park of SEONGNAM-SI (KR)
YOUNGWOONG Son of SUWON-SI (KR)
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 17872143 titled 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
Simplified Explanation
The patent application describes a semiconductor device that includes cell transistors, lower electrodes, and an etching stop layer.
- The cell transistors are located on a substrate.
- The lower electrodes are connected to the cell transistors and arranged in a first horizontal direction.
- The lower electrodes extend in a vertical direction.
- The etching stop layer surrounds the lower sidewalls of the lower electrodes and is positioned at a higher level than the cell transistors.
- The etching stop layer has two portions: a first portion that vertically overlaps the lower electrodes and a second portion that laterally surrounds the first portion.
- The second portion of the etching stop layer includes recesses arranged in a second pitch in the first horizontal direction.
Potential applications of this technology:
- Semiconductor manufacturing
- Electronics industry
- Integrated circuit production
Problems solved by this technology:
- Provides a structure that prevents etching damage to the lower electrodes during manufacturing processes.
- Ensures the integrity and functionality of the cell transistors.
Benefits of this technology:
- Improved manufacturing yield and reliability.
- Enhanced performance and functionality of semiconductor devices.
- Cost-effective production of integrated circuits.
Original Abstract Submitted
A semiconductor device includes; cell transistors on a substrate, lower electrodes respectively connected to the cell transistors, arranged according to a first pitch in a first horizontal direction, and extending in a vertical direction, and an etching stop layer surrounding lower sidewalls of the lower electrodes and arranged at a level higher than a level of the cell transistors, wherein the etching stop layer includes a first portion vertically overlapping the lower electrodes and a second portion laterally surrounding the first portion, and the second portion includes recesses arranged according to a second pitch in the first horizontal direction.
