17865811. SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

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SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Gyusik Kim of Suwon-si (KR)

Seungjin Kim of Yongin-si (KR)

Seunghyun Oh of Seoul (KR)

SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17865811 titled 'SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME

Simplified Explanation

The abstract describes a sub-sampling phase locked loop (PLL) system that includes various circuits and components to generate and control an output clock signal based on a reference clock signal. Here is a simplified explanation of the abstract:

  • The sub-sampling PLL includes a slope generating and sampling circuit, transconductance circuits, a constant transconductance bias circuit, a loop filter, and a voltage controlled oscillator.
  • The slope generating and sampling circuit generates a sampling voltage using the reference clock signal and the output clock signal.
  • The transconductance circuits generate output control voltages based on the sampling voltage, a reference voltage, and a control current.
  • The constant transconductance bias circuit includes a switched capacitor resistor and is responsible for generating the control current.
  • The loop filter is connected to the output terminals of the transconductance circuits.
  • The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.

Potential Applications:

  • This technology can be used in various applications that require precise synchronization of clocks, such as communication systems, data transmission, and digital signal processing.
  • It can also be utilized in high-speed data converters, frequency synthesizers, and other systems that require accurate timing.

Problems Solved:

  • The sub-sampling PLL solves the problem of accurately generating an output clock signal that is synchronized with a reference clock signal.
  • It addresses the challenges of maintaining stability and minimizing phase noise in clock synchronization systems.

Benefits:

  • The sub-sampling PLL provides improved accuracy and stability in generating output clock signals.
  • It offers a compact and efficient solution for clock synchronization, reducing the need for external components.
  • The technology enables high-speed data processing and transmission with minimal phase noise and timing errors.


Original Abstract Submitted

A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.

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