17858536. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Junghoon Kang of Anyang-si (KR)
Jihye Shim of Hwaseong-si (KR)
Jung Hyun Lee of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17858536 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor package that includes a lower substrate, a lower semiconductor chip, a lower mold layer, a redistribution layer, and a vertical connection terminal. The lower semiconductor chip has a cognition mark on its top surface, which includes a marking pattern with an intaglio shape and a molding pattern filling the inner space of the marking pattern. The molding pattern is made of the same material as the lower mold layer.
- A semiconductor package with a lower substrate, lower semiconductor chip, lower mold layer, redistribution layer, and vertical connection terminal is provided.
- The lower semiconductor chip has a cognition mark on its top surface.
- The cognition mark includes a marking pattern with an intaglio shape and a molding pattern filling the inner space of the marking pattern.
- The molding pattern is made of the same material as the lower mold layer.
Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
Problems Solved
- Provides a way to identify and recognize the lower semiconductor chip easily.
- Ensures compatibility between the molding pattern and the lower mold layer.
Benefits
- Simplifies the identification process of the lower semiconductor chip.
- Enhances the overall efficiency of semiconductor packaging.
- Reduces the risk of compatibility issues between different materials used in the package.
Original Abstract Submitted
A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.
