17851842. METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME
Organization Name
Inventor(s)
METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17851842 titled 'METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME
Simplified Explanation
The patent application describes a method for verifying a semiconductor device by generating different simulation environments for different blocks of the device and combining them for verification.
- The method involves receiving input data defining the semiconductor device, including multiple blocks.
- A first simulation environment is created for the top module and at least one target block of the device, which includes power wiring information and additional power-related information.
- A second simulation environment is generated for the non-target blocks of the device, which is different from the first simulation environment.
- The semiconductor device is then verified using a hybrid simulation environment that combines the first and second simulation environments.
Potential Applications
- Semiconductor industry
- Chip design and verification
Problems Solved
- Efficient verification of complex semiconductor devices with multiple blocks
- Simulating power-related information accurately
Benefits
- Improved accuracy in verifying semiconductor devices
- Time and resource savings in the verification process
- Enhanced understanding of power-related aspects of the device
Original Abstract Submitted
In a method of verifying a semiconductor device, input data defining the semiconductor device including a plurality of blocks is received. A first simulation environment is generated for a top module and at least one target block of the plurality of blocks in the top module. The first simulation environment includes power wiring information and additional power-related information. The top module represents an entire structure of the semiconductor device. A second simulation environment is generated for non-target blocks of the plurality of blocks other than the at least one target block. The second simulation environment is different from the first simulation environment. A verification operation is performed on the semiconductor device based on a hybrid simulation environment in which the first simulation environment and the second simulation environment are combined.
