17846967. ASYNCHRONOUS SIGNAL TO COMMAND TIMING CALIBRATION FOR TESTING ACCURACY simplified abstract (MICRON TECHNOLOGY, INC.)

ASYNCHRONOUS SIGNAL TO COMMAND TIMING CALIBRATION FOR TESTING ACCURACY

Organization Name

MICRON TECHNOLOGY, INC.

Inventor(s)

Yoshinori Fujiwara of Boise ID (US)

Kevin G. Werhane of Boise ID (US)

Jason M. Johnson of Boise ID (US)

Daniel S. Miller of Boise ID (US)

ASYNCHRONOUS SIGNAL TO COMMAND TIMING CALIBRATION FOR TESTING ACCURACY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17846967 titled 'ASYNCHRONOUS SIGNAL TO COMMAND TIMING CALIBRATION FOR TESTING ACCURACY

Simplified Explanation

The patent application describes a delay circuit that is connected to a memory device. The delay circuit is located within the memory banks of the memory chips and is used to synchronize an asynchronous signal with an internal command signal received by each memory bank. This synchronization improves the accuracy of internal test operations.

• The delay circuit is integrated into the memory banks of the memory device.
• It calibrates the asynchronous signal received by each memory bank.
• The calibrated asynchronous signal is synchronized with the internal command signal received by each memory bank.
• This synchronization ensures a common timing relationship between the calibrated asynchronous signal and the internal command signal.
• The calibrated asynchronous signals are used in internal test operations to enhance testing accuracy.

Potential Applications

• Memory testing and calibration in electronic devices.
• Improving the accuracy of internal test operations in memory devices.

Problems Solved

• Asynchronous signals in memory devices can cause timing issues and inaccuracies in internal test operations.
• Synchronizing the asynchronous signals with internal command signals improves the accuracy of testing.

Benefits

• Enhanced accuracy in memory testing and calibration.
• Improved reliability of internal test operations in memory devices.

Original Abstract Submitted

A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.