17827126. RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
Hyunyoon Cho of Uiwang-Si (KR)
Junghwan Choi of Hwaseong-si (KR)
RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17827126 titled 'RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME
Simplified Explanation
The patent application describes a receiver for a multi-level signal, which includes a pre-amplifier circuit, a slicer circuit, and a decoder circuit.
- The pre-amplifier circuit generates intermediate data signals using the input data signal and reference voltages.
- The slicer circuit generates decision signals based on the intermediate data signals and a clock signal.
- The decoder circuit generates output data based on the decision signals.
The pre-amplifier circuit consists of two circuits with different structures, each generating intermediate data signals using different reference voltages.
Potential Applications
- This technology can be applied in communication systems that use multi-level signals, such as high-speed data transmission.
- It can be used in digital audio and video receivers to improve signal quality and accuracy.
Problems Solved
- The receiver addresses the challenge of accurately decoding multi-level signals by using a pre-amplifier circuit to generate intermediate data signals.
- The use of different reference voltages and circuit structures helps in improving the accuracy of the receiver.
Benefits
- The receiver provides improved signal quality and accuracy by generating intermediate data signals and decision signals.
- The use of different circuit structures and reference voltages allows for better optimization and performance of the receiver.
Original Abstract Submitted
A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.
