17721707. VIDEO DECODING APPARATUS AND METHOD simplified abstract (Samsung Electronics Co., Ltd.)
Contents
VIDEO DECODING APPARATUS AND METHOD
Organization Name
Inventor(s)
VIDEO DECODING APPARATUS AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 17721707 titled 'VIDEO DECODING APPARATUS AND METHOD
Simplified Explanation
The abstract describes a video decoding apparatus that includes a central processing unit (CPU) and a decoder. The CPU parses header data from an input bit-stream and generates a register set based on the parsed data. The decoder then decodes the input bit-stream using the input parameters obtained from the register set. While the decoder is decoding the first frame, the CPU simultaneously parses header data from a second bit-stream of the second frame.
- The video decoding apparatus includes a CPU and a decoder.
- The CPU parses header data from an input bit-stream and generates a register set.
- The decoder decodes the input bit-stream using the input parameters from the register set.
- The CPU can simultaneously parse header data from a second bit-stream while the decoder is decoding the first frame.
Potential Applications
- Video decoding in multimedia devices such as smartphones, tablets, and smart TVs.
- Streaming services that require efficient video decoding for smooth playback.
- Video conferencing systems that need real-time decoding of video streams.
Problems Solved
- Efficient parsing of header data in video bit-streams.
- Simultaneous parsing of header data for multiple frames.
- Improved performance and speed in video decoding.
Benefits
- Faster video decoding process.
- Improved efficiency in parsing header data.
- Simultaneous processing of multiple frames.
- Enhanced performance and smoother video playback.
Original Abstract Submitted
According to an example embodiment, a video decoding apparatus may be provided. The video decoding apparatus may include a central processing unit (CPU) configured to parse first header data included in an input bit-stream and generate a first register set based on the parsed first header data; and a decoder configured to decode the input bit-stream based on input parameters obtained through the first register set, wherein CPU is configured to parse second header data included in a second bit-stream of the input bit-stream of a second frame subsequent to the first frame while the decoder decodes a first bit-stream corresponding to the first frame.
