View source for 17698476. METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING POROUS DIELECTRIC LAYER AND SEMICONDUCTOR DEVICE FABRICATED THEREBY simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING POROUS DIELECTRIC LAYER AND SEMICONDUCTOR DEVICE FABRICATED THEREBY=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Jongcheon Kim of Seoul (KR)|Jongcheon Kim of Seoul (KR)]][[Category:Jongcheon Kim of Seoul (KR)]]

[[:Category:Hyunchul Lee of Hwaseong-si (KR)|Hyunchul Lee of Hwaseong-si (KR)]][[Category:Hyunchul Lee of Hwaseong-si (KR)]]

[[:Category:Ki-Jeong Kim of Seongnam-si (KR)|Ki-Jeong Kim of Seongnam-si (KR)]][[Category:Ki-Jeong Kim of Seongnam-si (KR)]]

[[:Category:Donghwi Shin of Yongin-si (KR)|Donghwi Shin of Yongin-si (KR)]][[Category:Donghwi Shin of Yongin-si (KR)]]

[[:Category:Hyun-Sil Hong of Hwaseong-si (KR)|Hyun-Sil Hong of Hwaseong-si (KR)]][[Category:Hyun-Sil Hong of Hwaseong-si (KR)]]

==METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING POROUS DIELECTRIC LAYER AND SEMICONDUCTOR DEVICE FABRICATED THEREBY - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17698476 titled 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING POROUS DIELECTRIC LAYER AND SEMICONDUCTOR DEVICE FABRICATED THEREBY

==Simplified Explanation==

The patent application describes a method of fabricating a semiconductor device using a specific sequence of steps and materials. The method involves stacking multiple layers on a substrate and etching them to form patterns and grooves. The device fabricated using this method includes interconnection patterns in the grooves.

* The method involves stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate.
* The second mask layer is etched to form preliminary mask patterns.
* The preliminary mask patterns are further etched to form second mask patterns.
* The first mask layer is etched using the second mask patterns as an etch mask to form first mask patterns.
* The porous dielectric layer is etched using the first mask patterns as an etch mask to form grooves.
* Interconnection patterns are formed in the grooves.

Potential applications of this technology:

* Fabrication of semiconductor devices
* Integrated circuits
* Microprocessors
* Memory devices

Problems solved by this technology:

* Provides a method for fabricating semiconductor devices with improved interconnection patterns
* Enables the formation of grooves in a porous dielectric layer for interconnection patterns

Benefits of this technology:

* Improved performance and reliability of semiconductor devices
* Enhanced integration of components in integrated circuits
* Increased efficiency of microprocessors and memory devices


==Original Abstract Submitted==

A method of fabricating a semiconductor device and a device fabricated thereby, the method including sequentially stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate; etching the second mask layer to form preliminary mask patterns; etching the preliminary mask patterns to form second mask patterns; etching the first mask layer using the second mask patterns as an etch mask to form first mask patterns; etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves; and forming interconnection patterns in the grooves, respectively, wherein the porous dielectric layer includes SiOCH, and the first mask layer includes carbon-free silicon oxide (SiO).



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