17657822. Adjusting the Profile of Source/Drain Regions to Reduce Leakage simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

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Adjusting the Profile of Source/Drain Regions to Reduce Leakage

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Tsz-Mei Kwok of Hsinchu (TW)

Yung-Chun Yang of New Taipei City (TW)

Cheng-Yen Wen of Taichung (TW)

Li-Li Su of Chubei City (TW)

Yee-Chia Yeo of Hsinchu (TW)

Adjusting the Profile of Source/Drain Regions to Reduce Leakage - A simplified explanation of the abstract

This abstract first appeared for US patent application 17657822 titled 'Adjusting the Profile of Source/Drain Regions to Reduce Leakage

Simplified Explanation

The patent application describes a method for forming a semiconductor stack with sacrificial layers and nanostructures, and then creating a source/drain region with epitaxial layers of different dopant concentrations.

  • The method involves forming a protruding semiconductor stack with alternating sacrificial layers and nanostructures.
  • A dummy gate structure is formed on the stack, and then the stack is etched to create a source/drain recess.
  • First epitaxial layers are grown on the sidewalls of the nanostructures, with a quadrilateral shape in cross-section.
  • These first epitaxial layers have a lower dopant concentration.
  • A second epitaxial layer is then grown on top of the first epitaxial layers, with a higher dopant concentration.

Potential applications of this technology:

  • This method can be used in the fabrication of semiconductor devices, such as transistors.
  • It can improve the performance and efficiency of these devices by creating a source/drain region with controlled dopant concentrations.

Problems solved by this technology:

  • The method provides a simplified and efficient way to form a source/drain region with epitaxial layers.
  • It allows for precise control of the dopant concentration in the source/drain region.

Benefits of this technology:

  • The method enables the creation of semiconductor devices with improved performance and efficiency.
  • It offers a cost-effective and scalable approach for manufacturing these devices.
  • The controlled dopant concentration in the source/drain region enhances the electrical properties of the devices.


Original Abstract Submitted

A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.