View source for 17535359. PERFORMING BRANCH PREDICTOR TRAINING USING PROBABILISTIC COUNTER UPDATES IN A PROCESSOR simplified abstract (Microsoft Technology Licensing, LLC)

=PERFORMING BRANCH PREDICTOR TRAINING USING PROBABILISTIC COUNTER UPDATES IN A PROCESSOR=


==Organization Name==

[[:Category:Microsoft Technology Licensing, LLC|Microsoft Technology Licensing, LLC]]


[[Category:Microsoft Technology Licensing, LLC]]

==Inventor(s)==

[[:Category:Rami Mohammad Al Sheikh of Morrisville NC (US)|Rami Mohammad Al Sheikh of Morrisville NC (US)]][[Category:Rami Mohammad Al Sheikh of Morrisville NC (US)]]

[[:Category:Michael Scott Mcilvaine of Raleigh NC (US)|Michael Scott Mcilvaine of Raleigh NC (US)]][[Category:Michael Scott Mcilvaine of Raleigh NC (US)]]

[[:Category:Daren Eugene Streett of Cary NC (US)|Daren Eugene Streett of Cary NC (US)]][[Category:Daren Eugene Streett of Cary NC (US)]]

==PERFORMING BRANCH PREDICTOR TRAINING USING PROBABILISTIC COUNTER UPDATES IN A PROCESSOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17535359 titled 'PERFORMING BRANCH PREDICTOR TRAINING USING PROBABILISTIC COUNTER UPDATES IN A PROCESSOR

==Simplified Explanation==

The patent application describes a method for training a branch predictor in a processor using probabilistic counter updates. The branch predictor training circuit determines the accuracy of a branch prediction and updates the corresponding counter in a branch predictor table based on the accuracy.

* The branch predictor training circuit determines if a branch prediction is correct.
* The first counter in the branch predictor table is probabilistically updated based on the accuracy of the branch prediction.
* The update of the first counter can be based on a global probability value or a table-specific probability value.

Potential applications of this technology:

* Processors in computers and mobile devices can benefit from improved branch prediction accuracy.
* This technology can enhance the performance and efficiency of processors in various applications, such as gaming, artificial intelligence, and data processing.

Problems solved by this technology:

* Branch prediction accuracy is crucial for efficient execution of instructions in a processor.
* Traditional branch predictors may not always provide accurate predictions, leading to performance degradation.
* This technology addresses the problem by probabilistically updating the counters in the branch predictor table, improving the accuracy of branch predictions.

Benefits of this technology:

* Improved branch prediction accuracy leads to better performance and efficiency of processors.
* Probabilistic counter updates allow for adaptive and dynamic training of the branch predictor.
* The use of global and table-specific probability values provides flexibility in updating the counters, optimizing the branch prediction process.


==Original Abstract Submitted==

Performing branch predictor training using probabilistic counter updates in a processor is disclosed herein. In some aspects, a branch predictor training circuit of a processor is configured to determine whether a first branch prediction generated for a first conditional branch instruction by a branch predictor circuit of the processor is correct. Based on determining whether the first branch prediction is correct, the branch predictor training circuit probabilistically updates a first counter, corresponding to the first branch prediction, of a plurality of counters of a first branch predictor table of a plurality of branch predictor tables. In some aspects, the branch predictor training circuit probabilistically updates the first counter based on a global probability value corresponding to all branch predictor tables, while in some aspects the branch predictor training circuit is configured to probabilistically update the first counter based on a table-specific probability value corresponding to the first branch predictor table.



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