US Patent Application 17739871. MEMORY DEVICE AND METHOD FOR FORMING THE SAME simplified abstract

MEMORY DEVICE AND METHOD FOR FORMING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Kuan-Ting Chen of Taichung City (TW)

Chun-Yu Liao of Taipei City (TW)

Kuo-Yu Hsiang of Kaohsiung City (TW)

Yun-Fang Chung of Miaoli County (TW)

Min-Hung Lee of Taipei City (TW)

Shu-Tong Chang of Taoyuan City (TW)

MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17739871 titled 'MEMORY DEVICE AND METHOD FOR FORMING THE SAME

Simplified Explanation

The patent application describes a method for fabricating a semiconductor device with a ferroelectric gate structure. The method involves several steps, including depositing layers of ferroelectric and dielectric materials, patterning them to form a gate structure, and forming source/drain regions.

• Method for fabricating a semiconductor device with a ferroelectric gate structure
• Formation of a semiconductor layer over a substrate
• Deposition of a first ferroelectric layer over a channel region of the semiconductor layer
• Deposition of a first dielectric layer over the first ferroelectric layer
• Deposition of a second ferroelectric layer over the first dielectric layer
• Deposition of a gate metal layer over the second ferroelectric layer
• Patterning of the gate metal layer, second ferroelectric layer, first dielectric layer, and first ferroelectric layer to form a gate structure
• Formation of source/drain regions in the semiconductor layer on opposite sides of the gate structure

Original Abstract Submitted

A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.