US Patent Application 18225114. SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract

SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Ta-Chun Lin of Hsinchu (TW)

Kuo-Hua Pan of Hsinchu (TW)

Jhon Jhy Liaw of Hsinchu (TW)

SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18225114 titled 'SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME

Simplified Explanation

The patent application describes a semiconductor structure with two semiconductor devices formed over a substrate.

• The first semiconductor device includes a first source/drain feature, a first gate structure, a first conductive feature, and a first insulation layer.
• The first insulation layer contains a first contact etching stop layer (CESL) in contact with the first source/drain feature.
• The second semiconductor device includes a second source/drain feature, a second gate structure, a second conductive feature, and a second insulation layer.
• The second insulation layer contains a second CESL in contact with the second source/drain feature.
• The thickness of the first CESL is smaller than the thickness of the second CESL.

Original Abstract Submitted

A semiconductor structure includes a first semiconductor device formed over a substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature. The semiconductor structure includes a second semiconductor device formed over the substrate, including a second source/drain feature over the substrate, a second gate structure over the substrate, a second conductive feature over the second source/drain feature, and a second insulation layer between the second gate structure and the second conductive feature, the second insulation layer comprises a second CESL in contact with the second source/drain feature, wherein a thickness of the first CESL is less than a thickness of the second CESL.