US Patent Application 17662366. SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Hsien-Wei Chen of Hsinchu City (TW)
Meng-Liang Lin of Hsinchu (TW)
SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17662366 titled 'SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING
Simplified Explanation
- The patent application describes a semiconductor package that is used in high-performance computing. - The package includes an interposer, which is a component that connects the integrated circuit die to the substrate. - A spacer structure is mounted to the bottom surface of the interposer. - The spacer structure is designed to maintain a clearance between the integrated circuit die and the substrate. - This clearance reduces the likelihood of interference or collision between the die and the substrate, which could cause damage. - By reducing the likelihood of damage, the reliability and yield of the semiconductor package are improved. - The spacer structure also improves the electrical connection between the die and the interposer, increasing its robustness. - Overall, the innovation aims to reduce the likelihood of damage to the die and substrate, while improving the reliability and yield of the semiconductor package.
Original Abstract Submitted
A semiconductor package, which may correspond to a high-performance computing package, includes an interposer over a substrate. A spacer structure is mounted to a bottom surface of the interposer. The spacer structure is configured to maintain a clearance between a bottom surface of an integrated circuit die mounted to the bottom surface of the interposer and a top surface of the substrate to reduce a likelihood of an interference or collision between the integrated circuit die and the substrate. In this way, a likelihood of damage to the integrated circuit die and/or the substrate is reduced. Additionally, a robustness of an electrical connection between the integrated circuit die and the interposer may increase to improve a reliability and/or a yield of the semiconductor package including the spacer structure.
