18523840. SiC EPITAXIAL WAFER simplified abstract (RESONAC CORPORATION)
Contents
- 1 SiC EPITAXIAL WAFER
SiC EPITAXIAL WAFER
Organization Name
Inventor(s)
Rimpei Kindaichi of Tokyo (JP)
Tamotsu Yamashita of Tokyo (JP)
SiC EPITAXIAL WAFER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18523840 titled 'SiC EPITAXIAL WAFER
Simplified Explanation
The abstract describes a patent application for a SiC epitaxial wafer with a SiC substrate and an epitaxial layer on one surface, where the substrate has a diameter of 195 mm or more and a warp of 50 μm or less.
- SiC epitaxial wafer with SiC substrate and epitaxial layer
- SiC substrate diameter of 195 mm or more
- Warp of 50 μm or less
Potential Applications
The technology can be used in:
- Power electronics
- High-temperature applications
- Aerospace industry
Problems Solved
This technology addresses issues related to:
- Warping in SiC wafers
- Enhancing performance in high-power devices
- Improving reliability in extreme conditions
Benefits
The benefits of this technology include:
- Improved wafer quality
- Enhanced device performance
- Increased reliability and durability
Potential Commercial Applications
Potential commercial applications include:
- Semiconductor manufacturing
- Power electronics industry
- Aerospace and defense sector
Possible Prior Art
One possible prior art could be the development of SiC wafers with smaller diameters and higher warping levels.
Unanswered Questions
How does this technology compare to traditional SiC wafers in terms of performance and cost?
This article does not provide a direct comparison between this technology and traditional SiC wafers in terms of performance and cost. Further research and analysis would be needed to determine the specific advantages and disadvantages of this innovation in comparison to existing solutions.
What are the specific manufacturing processes involved in producing these SiC epitaxial wafers with low warp levels?
The article does not delve into the specific manufacturing processes used to produce these SiC epitaxial wafers with low warp levels. Understanding the manufacturing techniques and processes involved could provide valuable insights into the feasibility and scalability of this technology.
Original Abstract Submitted
A SiC epitaxial wafer including: a SiC substrate; and a SiC epitaxial layer stacked on one surface of the SiC substrate, wherein a diameter of the SiC substrate is 195 mm or more, and a warp is 50 μm or less.
