17932907. SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING simplified abstract (SanDisk Technologies LLC)
Contents
- 1 SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING
Organization Name
Inventor(s)
Michiaki Sano of Milpitas CA (US)
Tatsuya Hinoue of Campbell CA (US)
SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17932907 titled 'SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING
Simplified Explanation
A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process is performed to form peripheral discrete via cavities, which are then expanded to form a continuous moat trench. An edge seal structure is formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed before the patterned conductive hard mask layer, and a moat trench can be formed around the periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during the anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.
- Conductive hard mask layer patterned with peripheral discrete openings
- Anisotropic etch process to form peripheral discrete via cavities
- Expansion of cavities to form a continuous moat trench
- Formation of an edge seal structure in the moat trench
- Option for a conductive bridge structure for electrical connection
- Electrical connection of the hard mask layer to the semiconductor substrate
Potential Applications
The technology described in this patent application could be applied in semiconductor manufacturing processes, specifically in the creation of intricate patterns and structures on semiconductor devices.
Problems Solved
This technology helps in reducing or preventing arcing during the etching process, ensuring the integrity of the semiconductor devices being manufactured.
Benefits
The benefits of this technology include improved manufacturing efficiency, enhanced device performance, and increased reliability of semiconductor products.
Potential Commercial Applications
The technology could find applications in the semiconductor industry for the production of advanced electronic devices with complex structures and patterns.
Possible Prior Art
Prior art in this field may include similar methods for patterning and etching conductive layers in semiconductor manufacturing processes.
Unanswered Questions
How does this technology compare to existing methods for patterning conductive layers in semiconductor devices?
This article does not provide a direct comparison with existing methods, leaving the reader to wonder about the specific advantages and limitations of this new approach.
What are the potential challenges or limitations of implementing this technology in large-scale semiconductor manufacturing facilities?
The article does not address the practical aspects of implementing this technology on an industrial scale, leaving room for speculation on the challenges that may arise.
Original Abstract Submitted
A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.
