18105792. SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM simplified abstract (ADVANTEST CORPORATION)
Contents
- 1 SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM
Organization Name
Inventor(s)
Edmundo De La Puente of San Jose CA (US)
SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM - A simplified explanation of the abstract
This abstract first appeared for US patent application 18105792 titled 'SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM
Simplified Explanation
Embodiments of the present invention involve a system that can selectively enable 16 lane or 8 lane device testing using multiplexor circuitry between a CXL1.1 CPU and the devices under test (DUTs) during testing. This allows for improved parallelism and testing efficiency compared to existing methods that can only test devices using 8 lanes of the CXL 1.1 CPU.
- Selectively enable 16 lane or 8 lane device testing
- Use multiplexor circuitry between CXL1.1 CPU and DUTs
- Improve parallelism and testing efficiency
- Enhance testing capabilities compared to existing methods
Potential Applications
This technology can be applied in various industries such as semiconductor testing, hardware development, and quality assurance processes.
Problems Solved
1. Limited testing capabilities with existing methods 2. Inefficient use of CPU lanes during device testing
Benefits
1. Improved parallelism 2. Enhanced testing efficiency 3. Increased flexibility in device testing
Potential Commercial Applications
Optimizing CPU lane usage for device testing in semiconductor manufacturing
Possible Prior Art
One possible prior art could be the use of multiplexor circuitry in testing systems, but the specific application of selectively enabling 16 or 8 lane device testing may be novel.
Unanswered Questions
1. How does this technology impact the overall cost of device testing? 2. Are there any limitations to the types of devices that can be tested using this system?
Original Abstract Submitted
Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.
