18229965. LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE simplified abstract (ADVANTEST CORPORATION)
Contents
- 1 LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE
Organization Name
Inventor(s)
Edmundo De La Puente of San Jose CA (US)
Linden Hsu of San Jose CA (US)
Mei-Mei Su of San Jose CA (US)
Marilyn Kushnick of San Jose CA (US)
LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18229965 titled 'LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE
Simplified Explanation
The tester system described in the abstract is a system that includes a test computer system and a hardware interface module for testing multiple devices under test (DUTs). The hardware interface module is capable of applying test input signals to the DUTs and receiving test output signals from them. The system also includes a high-performance processor in the hardware interface module for performing testing functionality at high speed, under control of instructions and data from memory and software commands from the test computer system. Additionally, a low power module is included in the system for operating in low power mode, with the high-performance processor directing the low power module to configure the DUTs into low power mode for testing.
- The tester system includes a test computer system and a hardware interface module for testing multiple devices under test (DUTs).
- The hardware interface module is equipped with a high-performance processor for high-speed testing functionality.
- A low power module is included in the system for operating in low power mode during testing.
Potential Applications
The technology described in this patent application could be used in various industries such as electronics manufacturing, telecommunications, and automotive for testing and quality control of electronic devices.
Problems Solved
This technology solves the problem of efficiently testing multiple devices under test while conserving power and ensuring accurate results.
Benefits
The benefits of this technology include high-speed testing functionality, low power operation, and accurate testing results for multiple devices under test.
Potential Commercial Applications
Potential commercial applications of this technology include test equipment manufacturing, electronics testing services, and quality control systems for electronic device production.
Possible Prior Art
One possible prior art for this technology could be automated test equipment systems used in electronics manufacturing for testing electronic components and devices.
Original Abstract Submitted
A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.
