US Patent Application 18126761. SRAM DEVICE AND 3D SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF simplified abstract
Contents
SRAM DEVICE AND 3D SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF
Organization Name
Inventor(s)
Ho Young Tang of Suwon-si (KR)
Tae-Hyung Kim of Suwon-si (KR)
Dae Young Moon of Suwon-si (KR)
Sang-Yeop Baeck of Suwon-si (KR)
Dong-Wook Seo of Suwon-si (KR)
SRAM DEVICE AND 3D SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18126761 Titled 'SRAM DEVICE AND 3D SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF'
Simplified Explanation
The abstract describes a three-dimensional semiconductor integrated circuit and a static random access memory (SRAM) device. The circuit includes multiple dies, with the first die containing a power supply circuit, the second die containing an SRAM with a through-silicon-via (TSV) bundle region, and the third die containing a processor. The TSVs connect the TSV bundle region to the third die. The SRAM device consists of a bank array with sub-bit-cell arrays and a local peripheral circuit region arranged in a cross shape. It also includes a global peripheral circuit region with a tail peripheral circuit region extending in one direction and a head peripheral circuit region extending in another direction, forming a T shape.
Original Abstract Submitted
Provided are a three-dimensional (3D) semiconductor integrated circuit and a static random access memory (SRAM) device. The three-dimensional (3D) semiconductor integrated circuit includes: a first die including a power supply circuit a second die including an SRAM with a through-silicon-via (TSV) bundle region; a third die including a processor; and TSVs, each of which is provided on the TSV bundle region and extends from the TSV bundle region to the third die. The SRAM device includes: a bank array with banks, each of which includes sub-bit-cell arrays and a local peripheral circuit region arranged in a cross (+) shape between the sub-bit-cell arrays; and a global peripheral circuit region including a tail peripheral circuit region extending in a first direction and a head peripheral circuit region extending in a second direction, the tail peripheral circuit region and the head peripheral circuit region being arranged in a “T” shape.
