17942143. Mitigation of transistor reliability degradation within memory circuits simplified abstract (Apple Inc.)
Contents
- 1 Mitigation of transistor reliability degradation within memory circuits
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Mitigation of transistor reliability degradation within memory circuits - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Original Abstract Submitted
Mitigation of transistor reliability degradation within memory circuits
Organization Name
Inventor(s)
Assaf Shappir of Ganey Tikva (IL)
Mitigation of transistor reliability degradation within memory circuits - A simplified explanation of the abstract
This abstract first appeared for US patent application 17942143 titled 'Mitigation of transistor reliability degradation within memory circuits
Simplified Explanation
The controller described in the patent application monitors memory cells for errors and adjusts supply voltage to compensate for physical degradation of select transistors.
- Interface and circuitry in the controller communicate with memory cells in multiple address locations.
- Storage nodes in memory cells are accessed using select transistors powered by an adjustable supply voltage.
- Circuitry reads data units protected by an Error Correction Code (ECC) from memory cells and decodes the ECC.
- Upon detecting errors in data units, the controller logs error events with time of occurrence and address location.
- The controller identifies physical degradation of select transistors based on logged error events and adjusts supply voltage accordingly.
Potential Applications
This technology could be applied in:
- Data storage systems
- Computer memory modules
- Embedded systems
Problems Solved
This technology addresses issues related to:
- Memory errors
- Physical degradation of select transistors
- Data integrity in memory systems
Benefits
The benefits of this technology include:
- Improved data reliability
- Extended lifespan of memory systems
- Enhanced error correction capabilities
Potential Commercial Applications
Optimizing Supply Voltage for Select Transistors in Memory Systems
Original Abstract Submitted
A controller includes an interface and circuitry. The interface communicates with memory cells arranged in multiple address locations. Storage nodes holding storage values included in the memory cells are accessible using select transistors powered by an adjustable supply voltage. The circuitry reads data units protected by an Error Correction Code (ECC) from the memory cells and decode the ECC of the data units. Upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, the circuitry logs an error event specifying at least a time of occurrence associated with the error event and the given address location. The circuitry identifies that the select transistors experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events, and adjusts the supply voltage provided to the select transistors to compensate for the physical degradation.
