17886472. FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Kuo-Chang Chiang of Hsinchu City (TW)

Yu-Chuan Shih of Hsinchu City (TW)

Chun-Chieh Lu of Taipei City (TW)

Po-Ting Lin of Taichung City (TW)

Hai-Ching Chen of Hsinchu City (TW)

Sai-Hooi Yeong of Hsinchu County (TW)

Yu-Ming Lin of Hsinchu City (TW)

Chung-Te Lin of Tainan City (TW)

FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17886472 titled 'FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME

Simplified Explanation

The abstract describes a ferroelectric memory device with specific layers and electrodes arranged in a certain configuration.

• Gate electrode
• Ferroelectric layer on the gate electrode
• Channel layer on the ferroelectric layer
• Pair of source/drain (S/D) electrodes on the channel layer
• First insertion layer between the gate electrode and the ferroelectric layer
• Second insertion layer between the ferroelectric layer and the channel layer, with a thickness less than the first insertion layer

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1. 1. 1. Potential Applications

• Non-volatile memory devices
• High-speed data storage
• Embedded memory in integrated circuits

1. 1. 1. Problems Solved

• Improves data retention in memory devices
• Enhances performance and reliability of memory devices
• Reduces power consumption in memory devices

1. 1. 1. Benefits

• Increased memory device efficiency
• Enhanced data storage capabilities
• Improved overall performance of electronic devices

Original Abstract Submitted

Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.