SK hynix Inc. patent applications on January 2nd, 2025
Patent Applications by SK hynix Inc. on January 2nd, 2025
SK hynix Inc.: 21 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (5), H10B43/10 (3), H10N70/00 (2), H10B61/00 (2), H01L21/768 (2) H10B43/27 (3), G06F3/0659 (1), H01L23/562 (1), H10N50/20 (1), H10B61/00 (1)
With keywords such as: layer, structure, memory, line, device, configured, signal, direction, conductive, and pattern in patent application abstracts.
Patent Applications by SK hynix Inc.
20250004667. STORAGE DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Young Jin BAEK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: provided herein may be a storage device and a method of operating the same. the storage device may include a memory device including a plurality of memory blocks, and a memory controller configured to control the memory device to perform a read operation of reading data stored in a memory block selected from the plurality of memory blocks, and to obtain a compensated read count based on a unit read count, indicating a number of times the read operation is performed for a unit time, and a temperature measured for the unit time.
Inventor(s): Ku Ik KWON of Gyeonggi-do (KR) for sk hynix inc., Byoung Min JIN of Gyeonggi-do (KR) for sk hynix inc., Gyu Yeul HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F9/38, G06F9/48
CPC Code(s): G06F9/3838
Abstract: a data storage system includes a controller comprising pipelined multiple processors. the controller is configured to: generate plural instructions having dependency based on a command, input from an external device, for controlling at least one storage device to perform an operation corresponding to the command; allocate the plural instructions to the pipelined multiple processors in stages; and reallocate, when a number of second instructions allocated to a second processor of the pipelined multiple processors becomes a first threshold or greater, at least one of the second instructions to a first processor of the multiple processors.
Inventor(s): Bu Yong SONG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a storage device includes a memory device including a plurality of planes each including a plurality of memory blocks, and a controller configured to group the memory blocks into a plurality of super blocks, each including memory blocks belonging to two or more planes operating in parallel, change mapping information so that a bad block included in a super block to be allocated during super block allocation is replaced with a replacement block of the same plane as the bad block, and delete the mapping information corresponding to the replacement block when an allocated super block is released. the memory blocks are divided into user memory blocks grouped into the super blocks and reserved memory blocks that are not grouped into the super blocks, and the replacement block is selected from memory blocks included in free super blocks of an empty status and the reserved memory blocks.
Inventor(s): Jun Seo JANG of Gyeonggi-do (KR) for sk hynix inc., Sung Hwa OK of Gyeonggi-do (KR) for sk hynix inc., Eun Ji CHOI of Gyeonggi-do (KR) for sk hynix inc., Jae Hyeong HONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/08, G11C7/10, G11C7/20
CPC Code(s): G11C7/08
Abstract: a transceiver includes a first inverter chain configured to deliver a signal in response to an enable signal and a second inverter chain which is coupled to the first inverter chain in parallel and configured to output a reset value of the signal in response to an inverted enable signal.
Inventor(s): Jung Hwan JI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Min Soo PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Geun Il LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/408
CPC Code(s): G11C11/40615
Abstract: a refresh circuit is configured to generate a counting signal by counting a refresh command and to generate a plurality of preliminary refresh cycle change signals by decoding the counting signal. the refresh circuit is also configured to change a refresh cycle based on one of the plurality of preliminary refresh cycle change signals and to perform a refresh operation.
Inventor(s): Ho Seok EM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/408, G11C11/4074
CPC Code(s): G11C11/4085
Abstract: a memory apparatus includes a first main word line signal, a second main word line signal, and a word line driver. the first main word line signal is coupled to a first sub-word line driver block including n sub-word line drivers. the second main word line signal is coupled to a second sub-word line driver block including n sub-word line drivers. the main word line driver is configured to selectively enable one of the first and second main word line signals.
Inventor(s): Jae Yeon Lee of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C13/00, H10B63/00, H10N70/00
CPC Code(s): G11C13/0028
Abstract: a semiconductor device may include a voltage generation circuit configured to generate a driving voltage in response to a voltage control signal, a row decoder configured to select at least one word line, among a plurality of word lines, in response to a row address signal, and configured to apply the driving voltage to the selected word line, a column decoder configured to select at least one bit line, among a specific bit line and a plurality of bit lines, in response to a column address signal and a control circuit configured to generate the voltage control signal, the row address signal, and the column address signal, and configured to control the column decoder to select the specific bit line and at least one of the plurality of bit lines in a firing operation.
Inventor(s): Su Han LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/08, G11C16/04
CPC Code(s): G11C16/08
Abstract: an address counter comprises a flop-flop for performing a load operation of loading a start column address signal, responsive to a first logic signal provided to the flip-flop set terminal and a second logic signal provided to a reset terminal and for performing a counting operation of sequentially increasing a data value of the start column address signal.
Inventor(s): Dong Hun KWAK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/14
CPC Code(s): G11C16/3459
Abstract: a memory device includes a cell array and control circuitry. the cell array includes plural memory cells and plural switch transistors. the control circuitry is configured to perform checking and recovery operations regarding operating states of the plural switch transistors during operation margins set for the plural data input/output operations.
Inventor(s): Jong Seok JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/38, G11C29/02, G11C29/12
CPC Code(s): G11C29/38
Abstract: a test circuit including a test core configured to set a charging current quantity as a first value and perform charging and discharging on a test node of a test target circuit during a first measurement interval and configured to change the charging current quantity from the first value to a second value and perform charging and discharging on the test node during a second measurement interval, and an operation circuit configured to generate a first counting value by counting a clock signal during the first measurement interval, generate a second counting value by counting the clock signal during the second measurement interval, generate the results of an operation of the first counting value and the second counting value as operation results, and output at least one of the first counting value, the second counting value, and the operation results as test result information.
Inventor(s): Yun Cheol HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): H01L23/562
Abstract: there are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. the semiconductor memory device includes a stack structure including a cell array region and a contact region extending from the cell array region, a cell plug penetrating the cell array region of the stack structure, a conductive gate contact penetrating the contact region of the stack structure, and a plurality of first support structures bordering a perimeter of the conductive gate contact and disposed to be spaced apart from the center of the conductive gate contact at a first distance.
20250006801. METHOD FOR FABRICATING SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Young Gwang YOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/40, H01L21/311, H01L21/3213, H01L21/768
CPC Code(s): H01L29/401
Abstract: according to the embodiment of the present invention, it is possible to minimize the loss of the substrate that may be caused by the difference in etching height by taking advantage of the difference in the etch selectivity between a nitride material, an oxide material, and a conductive material, and minimizing the exposure of the substrate while each contact hole is formed. according to the embodiment of the present invention, a loss of the substrate may be minimized when contact holes having different etching depths are formed.
Inventor(s): Toshiaki NAGAI of Tokyo (JP) for sk hynix inc.
IPC Code(s): H04N25/705, G01S7/4865, G01S17/894, H04N25/44, H04N25/46
CPC Code(s): H04N25/705
Abstract: a depth image sensing device includes a line memory configured to store depth data, in units of a line group, generated by detecting a dot pattern light reflected from a scene, a dot center pixel detector configured to determine a dot center pixel having a highest intensity of depth data in each of a plurality of kernels included in the line group, and a dot data memory configured to store dot center pixel information including a position of the dot center pixel.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Jun Ha KWAK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: a semiconductor device includes: a lower structure; a plurality of horizontal layers horizontally oriented over the lower structure; a first conductive line commonly coupled to first ends of the horizontal layers and extending in a direction perpendicular to the lower structure; a plurality of second conductive lines crossing the horizontal layers, respectively; a plurality of data storage elements coupled to second ends of the horizontal layers, respectively, and stacked in a direction perpendicular to the lower structure; capping layers disposed between the second conductive lines and the first conductive line; and blocking layers disposed between the capping layers and the first conductive line.
Inventor(s): Yun Cheol HAN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/10, H10B41/10, H10B41/27, H10B43/27
CPC Code(s): H10B43/10
Abstract: a semiconductor device may include a gate structure including insulating layers and conductive layers that are alternately stacked, a real channel structure extending through the gate structure, a slit structure extending in a first direction along the sidewall of the gate structure, a contact structure extending through the gate structure and that is electrically connected to at least one conductive layer, among the conductive layers, and a pair of first supports extending in an arc form along the sidewall of the contact structure and that includes concave and convex parts on sidewalls of the first supports.
Inventor(s): Hyung Jun YANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Tae Soo JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a memory device may include a stack structure, comprised of layers of first and second materials, which are alternately stacked. the stack structure also include a channel layer inside the stack structure. the channel layer may include a first sub-channel layer, a liner layer formed along an inner wall of the first sub-channel layer, and a second sub-channel layer formed along an inner wall of the liner layer.
Inventor(s): Seok Min CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jeong Hwan KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a semiconductor device, and a method of manufacturing the same, includes a gate stack including a plurality of conductive lines extending in a first horizontal direction, a first slit and a second slit passing through the gate stack in a vertical direction and extending in the first horizontal direction, and a plurality of cell plugs extending in the vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. each of the first slit and the second slit includes a first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and a second portion extending in the first horizontal direction.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L21/768, H01L23/528, H10B41/27, H10B41/50, H10B43/50
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. the pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. the pad structure may have a plurality of stepped structures. the circuit may be disposed under the pad structure. the one or more openings may pass through the pad structure, and may expose the circuit. the one or more openings may be disposed between the plurality of stepped structures.
Inventor(s): Jong Min YUN of Icheon-si (KR) for sk hynix inc., Cha Deok DONG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B61/00, H10N50/01
CPC Code(s): H10B61/00
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes: a substrate; a pattern disposed over the substrate; a hard mask pattern that is conductive and disposed over the pattern, the hard mask pattern including a lower hard mask pattern and an upper hard mask pattern over the lower hard mask pattern; a conductive pattern disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern; and an insulating layer covering a sidewall of the pattern and a sidewall of the lower hard mask pattern, wherein the upper hard mask pattern is disposed to protrude from the insulating layer.
Inventor(s): Soo Man SEO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10N50/20, H01F10/32, H10B61/00
CPC Code(s): H10N50/20
Abstract: in an embodiment, a semiconductor device includes a spin orbit torque (sot) line extending in a first direction; an electrode layer spaced apart from the sot line in a third direction; and a magnetic tunnel junction structure interposed between the sot line and the electrode layer, and including a free layer adjacent to the sot line in the third direction, a pinned layer adjacent to the electrode layer in the third direction, and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the magnetic tunnel junction structure includes a first portion overlapping the sot line and a second portion not overlapping the sot line in a second direction, the electrode layer overlaps at least a portion of the second portion, and a thickness of the free layer in the first portion is greater than a thickness of the free layer in the second portion.
Inventor(s): Jeong Myeong KIM of Icheon-si (KR) for sk hynix inc., Cha Deok DONG of Icheon-si (KR) for sk hynix inc., Keo Rock CHOI of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/883
Abstract: a semiconductor device includes a plurality of memory cells. each memory cell includes: a first electrode layer; a second electrode layer; a memory layer electrically connected to the second electrode layer and configured to store data; a selector layer interposed between the first electrode layer and the second electrode layer and configured to control an access to the memory layer, the selector layer including an insulating material layer doped with a dopant, wherein at least one of the first electrode layer and the second electrode layer includes a first sub-electrode layer, and a second sub-electrode layer interposed between the first sub-electrode layer and the selector layer and including a material having a work function greater than a work function of the first sub-electrode layer.
- SK hynix Inc.
- G06F3/06
- CPC G06F3/0659
- Sk hynix inc.
- G06F9/38
- G06F9/48
- CPC G06F9/3838
- G06F12/02
- CPC G06F12/0246
- G11C7/08
- G11C7/10
- G11C7/20
- CPC G11C7/08
- G11C11/406
- G11C11/408
- CPC G11C11/40615
- G11C11/4074
- CPC G11C11/4085
- G11C13/00
- H10B63/00
- H10N70/00
- CPC G11C13/0028
- G11C16/08
- G11C16/04
- CPC G11C16/08
- G11C16/34
- G11C16/10
- G11C16/14
- CPC G11C16/3459
- G11C29/38
- G11C29/02
- G11C29/12
- CPC G11C29/38
- H01L23/00
- H10B43/10
- H10B43/27
- H10B43/35
- CPC H01L23/562
- H01L29/40
- H01L21/311
- H01L21/3213
- H01L21/768
- CPC H01L29/401
- H04N25/705
- G01S7/4865
- G01S17/894
- H04N25/44
- H04N25/46
- CPC H04N25/705
- H10B12/00
- CPC H10B12/30
- H10B41/10
- H10B41/27
- CPC H10B43/10
- CPC H10B43/27
- H01L23/528
- H10B41/50
- H10B43/50
- H10B61/00
- H10N50/01
- CPC H10B61/00
- H10N50/20
- H01F10/32
- CPC H10N50/20
- CPC H10N70/883
