17866517. MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE
Organization Name
Inventor(s)
Youngmin Jo of Hwaseong-si (KR)
Byunghoon Jeong of Suwon-si (KR)
MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17866517 titled 'MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE
Simplified Explanation
The abstract describes a memory package that includes multiple memory chips and an interface chip. The interface chip acts as a communication relay between a controller and the memory chips, and it also receives signals from the memory chips.
- The interface chip has receivers that output a data signal and a raw clock signal based on the signals from the memory chips.
- It also includes a delay circuit that applies an offset delay and an additional delay to the raw clock signal, generating a delay clock signal.
- A sampler in the interface chip samples the data signal in synchronization with a clock signal.
- The delay circuit adjusts the clock signal by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.
Potential applications of this technology:
- Memory packages used in various electronic devices such as computers, smartphones, and tablets.
- High-performance data storage systems that require efficient communication between memory chips and controllers.
Problems solved by this technology:
- Ensures accurate and synchronized communication between the controller and memory chips.
- Minimizes phase differences between clock signals and data signals, reducing data transmission errors.
Benefits of this technology:
- Improved data transmission reliability and accuracy.
- Enhanced performance of memory packages in terms of speed and efficiency.
- Enables the use of memory packages in high-performance computing systems.
Original Abstract Submitted
A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.
