17743233. MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Ken-Ichi Goto of Hsinchu (TW)

Cheng-Yi Wu of Taichung City (TW)

MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17743233 titled 'MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS

Simplified Explanation

The patent application describes a semiconductor device that includes multiple layers and structures to form various transistors. Here is a simplified explanation of the abstract:

• The semiconductor device consists of a substrate, a first layer, and a second layer.
• The first layer contains a fin structure, a gate structure overlapping the fin structure to create a pass-gate transistor, and another gate structure separate from the first one, overlapping the fin structure to form a pull-down transistor.
• The second layer includes a third gate structure connected to the second gate structure, a semiconductor oxide structure on the third gate structure, and drain/source regions on the oxide structure, forming a pull-up transistor.

Potential applications of this technology:

• Integrated circuits: The semiconductor device can be used in the production of integrated circuits, enabling the creation of complex electronic systems.
• Microprocessors: The device's multiple transistors can be utilized in the development of microprocessors, enhancing their performance and functionality.
• Memory devices: The technology can be employed in memory devices, improving their speed and capacity.

Problems solved by this technology:

• Enhanced transistor functionality: The device allows for the creation of different types of transistors, enabling more complex circuit designs and improved performance.
• Space efficiency: The layered structure of the device allows for the integration of multiple transistors in a compact space, optimizing the use of available area on a semiconductor chip.

Benefits of this technology:

• Improved performance: The various transistors formed by the device can enhance the speed, power efficiency, and overall performance of electronic systems.
• Compact design: The layered structure of the device enables the integration of multiple transistors in a smaller area, leading to more compact and efficient electronic devices.
• Versatility: The ability to create different types of transistors provides flexibility in circuit design, allowing for the development of more advanced and specialized electronic systems.

Original Abstract Submitted

A semiconductor device including a substrate, a first layer over the substrate, and a second layer over the first layer. The first layer including a first fin structure, a first gate structure that overlaps the first fin structure to form a first pass-gate transistor, and a second gate structure that is separate from the first gate structure and that overlaps the first fin structure to form a first pull-down transistor. The second layer including a third gate structure disposed over the second gate structure and connected to the second gate structure, a first semiconductor oxide structure disposed on the third gate structure, and a first drain/source region and a second drain/source region disposed on the first semiconductor oxide structure, wherein the third gate structure, the first semiconductor oxide structure, the first drain/source region, and the second drain/source region constitute a first pull-up transistor.