17832261. MEMORY DEVICE AND METHOD simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
MEMORY DEVICE AND METHOD
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Meng-Fan Chang of Taichung (TW)
MEMORY DEVICE AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 17832261 titled 'MEMORY DEVICE AND METHOD
Simplified Explanation
The abstract describes an Input/Output (I/O) circuit for a memory device. Here is a simplified explanation of the abstract:
- The I/O circuit is designed to work with a memory device and includes a charge integration circuit connected to a bitline of the memory device.
- The charge integration circuit is responsible for providing a sensing voltage based on a decrease in voltage on the bitline.
- A comparator is connected to the charge integration circuit and compares the sensing voltage with a reference voltage.
- Based on this comparison, the comparator generates an output voltage.
- A time-to-digital converter is connected to the comparator and converts the time associated with the output voltage into a digital value.
Potential applications of this technology:
- This I/O circuit can be used in various memory devices, such as RAM (Random Access Memory) or flash memory.
- It can be implemented in both standalone memory devices and integrated circuits.
Problems solved by this technology:
- The I/O circuit solves the problem of accurately sensing the voltage on the bitline of a memory device.
- It addresses the need for a reliable and efficient method of converting the output voltage into a digital value.
Benefits of this technology:
- The charge integration circuit provides a more accurate sensing voltage, leading to improved performance and reliability of the memory device.
- The time-to-digital converter allows for precise conversion of the output voltage into a digital value, enhancing the overall functionality of the memory device.
Original Abstract Submitted
An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.
